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1. 发明授权

US07687867B2 Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme 失效
标题翻译：制造更高性能的电容密度MIMcap的廉价方法可以集成到铜互连方案中
公开(公告)号：US07687867B2
公开(公告)日：2010-03-30
申请号：US11846248
申请日：2007-08-28
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , William J. Murphy , Vidhya Ramachandran
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , William J. Murphy , Vidhya Ramachandran
IPC分类号： H01L29/72
CPC分类号： H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode. The bottom and top plate electrodes can comprise the same or different conductive metal.
摘要翻译：提供了一种将MIM电容器集成到导电互连级别中的方法，具有低成本影响，并且提供了比现有集成方法高的产量，可靠性和性能。这通过将用于MIM电容器电平对准的先前级别的电介质凹入，然后MIM电容器膜的沉积和图案化来实现。具体地，该方法包括提供包括布线层的衬底，所述布线层包括形成在电介质层中的至少一个导电布线; 选择性地去除所述电介质层的一部分以使所述电介质层在所述至少一个导电互连的上表面下方凹陷; 在所述至少一个导电互连和所述凹入的介电层上形成电介质叠层; 以及在介电叠层上形成金属绝缘体金属（MIM）电容器。 MIM电容器包括底板电极，电介质和顶板电极。底板和顶板电极可以包括相同或不同的导电金属。

2. 发明授权

US07282404B2 Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme 有权
标题翻译：制造更高性能的电容密度MIMcap的廉价方法可以集成到铜互连方案中
公开(公告)号：US07282404B2
公开(公告)日：2007-10-16
申请号：US10709829
申请日：2004-06-01
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , William J. Murphy , Vidhya Ramachandran
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , William J. Murphy , Vidhya Ramachandran
IPC分类号： H01L21/8242
CPC分类号： H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode. The bottom and top plate electrodes can comprise the same or different conductive metal.
摘要翻译：提供了一种将MIM电容器集成到导电互连级别中的方法，具有低成本影响，并且提供了比现有集成方法高的产量，可靠性和性能。这通过将用于MIM电容器电平对准的先前级别的电介质凹入，然后MIM电容器膜的沉积和图案化来实现。具体地，该方法包括提供包括布线层的衬底，所述布线层包括形成在电介质层中的至少一个导电布线; 选择性地去除所述电介质层的一部分以使所述电介质层在所述至少一个导电互连的上表面下方凹陷; 在所述至少一个导电互连和所述凹入的介电层上形成电介质叠层; 以及在介电叠层上形成金属绝缘体金属（MIM）电容器。 MIM电容器包括底板电极，电介质和顶板电极。底板和顶板电极可以包括相同或不同的导电金属。

3. 发明授权

US07511940B2 Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask 失效
标题翻译：金属绝缘体金属电容器与铝金属布线层同时使用硬掩模形成
公开(公告)号：US07511940B2
公开(公告)日：2009-03-31
申请号：US11838939
申请日：2007-08-15
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Natalie B. Feilchenfeld , Michael L. Gautsch , Zhong-Xiang He , Matthew D. Moon , Vidhya Ramachandran , Barbara Waterhouse
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Natalie B. Feilchenfeld , Michael L. Gautsch , Zhong-Xiang He , Matthew D. Moon , Vidhya Ramachandran , Barbara Waterhouse
IPC分类号： H01G4/38
CPC分类号： H01L23/5223 , H01L27/016 , H01L27/0805 , H01L28/40 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.
摘要翻译：公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。在该方法中，在下导体层的上方形成电介质层，在电介质层的上方形成上导体层。然后，本发明在上导体层和电介质层之上形成蚀刻停止层，并在蚀刻停止层上形成硬掩模（氧化硅硬掩模，氮化硅硬掩模等）。接下来，在硬掩模上形成光致抗蚀剂，这允许通过光致抗蚀剂蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

4. 发明授权

US07301752B2 Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask 有权
标题翻译：金属绝缘体金属电容器与铝金属布线层同时使用硬掩模形成
公开(公告)号：US07301752B2
公开(公告)日：2007-11-27
申请号：US10709907
申请日：2004-06-04
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Natalie B. Feilchenfeld , Michael L. Gautsch , Zhong-Xiang He , Matthew D. Moon , Vidhya Ramachandran , Barbara Waterhouse
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Natalie B. Feilchenfeld , Michael L. Gautsch , Zhong-Xiang He , Matthew D. Moon , Vidhya Ramachandran , Barbara Waterhouse
IPC分类号： H01G4/38
CPC分类号： H01L23/5223 , H01L27/016 , H01L27/0805 , H01L28/40 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.
摘要翻译：公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。在该方法中，在下导体层的上方形成电介质层，在电介质层的上方形成上导体层。然后，本发明在上导体层和电介质层之上形成蚀刻停止层，并在蚀刻停止层上形成硬掩模（氧化硅硬掩模，氮化硅硬掩模等）。接下来，在硬掩模上形成光致抗蚀剂，这允许通过光致抗蚀剂蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

5. 发明授权

US06876028B1 Metal-insulator-metal capacitor and method of fabrication 有权
公开(公告)号：US06876028B1
公开(公告)日：2005-04-05
申请号：US10605444
申请日：2003-09-30
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Jeffrey P. Gambino , Zhong-Xiang He , Vidhya Ramachandran
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Jeffrey P. Gambino , Zhong-Xiang He , Vidhya Ramachandran
IPC分类号： H01L21/02 , H01L21/768 , H10L27/108 , H10L29/76 , H10L29/94 , H10L31/119
CPC分类号： H01L21/7687 , H01L23/5223 , H01L23/53238 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

6. 发明申请

US20110049674A1 INTERDIGITATED VERTICAL PARALLEL CAPACITOR 有权
标题翻译： INTERDIGITATED垂直并联电容器
公开(公告)号：US20110049674A1
公开(公告)日：2011-03-03
申请号：US12548484
申请日：2009-08-27
申请人： Roger A. Booth, Jr. , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He
发明人： Roger A. Booth, Jr. , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/90 , H01L23/5223 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.
摘要翻译：叉指结构可以包括至少一个第一金属线，平行于至少一个第一金属线并与至少一个第一金属线分离的至少一个第二金属线，以及接触至少一个第一金属线的端部的第三金属线第一金属线并且与所述至少一个第二金属线分离。所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。多层交错结构可以垂直堆叠。替代地，叉指结构可以包括多个第一金属线和多个第二金属线，每个金属线不垂直地接触任何金属通孔。交错结构的多个实例可以横向复制和邻接，具有或不具有旋转和/或垂直堆叠以形成电容器。

7. 发明授权

US07494912B2 Terminal pad structures and methods of fabricating same 有权
标题翻译：端子焊盘结构及其制造方法
公开(公告)号：US07494912B2
公开(公告)日：2009-02-24
申请号：US11953927
申请日：2007-12-11
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

8. 发明申请

US20080173981A1 INTEGRATED CIRCUIT (IC) CHIP WITH ONE OR MORE VERTICAL PLATE CAPACITORS AND METHOD OF MAKING THE CAPACITORS 审中-公开
标题翻译：具有一个或多个垂直板电容器的集成电路（IC）芯片和制造电容器的方法
公开(公告)号：US20080173981A1
公开(公告)日：2008-07-24
申请号：US11624712
申请日：2007-01-19
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L28/91 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An Integrated Circuit (IC) chip with one or more vertical plate capacitors, each vertical plate capacitor connected to circuits on the IC chip and a method of making the chip capacitors. The vertical plate capacitors are formed with base plate pattern (e.g., damascene copper) on a circuit layer and at least one upper plate layer (e.g., dual damascene copper) above, connected to and substantially identical with the base plate pattern. A vertical pair of capacitor plates are formed by the plate layer and base plate. Capacitor dielectric between the vertical pair of capacitor plates is, at least in part, a high-k dielectric.
摘要翻译：具有一个或多个垂直板电容器的集成电路（IC）芯片，每个垂直板电容器连接到IC芯片上的电路和制造芯片电容器的方法。垂直板电容器在电路层上形成有底板图案（例如，镶嵌铜），以及与基板图案连接并基本相同的至少一个上板层（例如双镶嵌铜）。一对电容器板由板层和底板形成。垂直对电容器板之间的电容电介质至少部分地是高k电介质。

9. 发明授权

US07382055B2 Integrated thin-film resistor with direct contact 有权
标题翻译：集成薄膜电阻直接接触
公开(公告)号：US07382055B2
公开(公告)日：2008-06-03
申请号：US11846595
申请日：2007-08-29
申请人： Eric M. Coker , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Matthew D. Moon , Anthony K. Stamper
发明人： Eric M. Coker , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Matthew D. Moon , Anthony K. Stamper
IPC分类号： H01L29/40
CPC分类号： H01L27/016
摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.
摘要翻译：适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

10. 发明授权

US08435864B2 Process for single and multiple level metal-insulator-metal integration with a single mask 有权
标题翻译：单层和多层金属绝缘体金属与单一掩模集成的工艺
公开(公告)号：US08435864B2
公开(公告)日：2013-05-07
申请号：US13432440
申请日：2012-03-28
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：提供一种制造MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

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