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1. 发明授权

US06516429B1 Method and apparatus for run-time deconfiguration of a processor in a symmetrical multi-processing system 失效
标题翻译：用于对称多处理系统中的处理器的运行时解配置的方法和装置
公开(公告)号：US06516429B1
公开(公告)日：2003-02-04
申请号：US09434767
申请日：1999-11-04
申请人： Douglas Craig Bossen , Alongkorn Kitamorn , Charles Andrew McLaughlin , John Thomas O'Quin, II
发明人： Douglas Craig Bossen , Alongkorn Kitamorn , Charles Andrew McLaughlin , John Thomas O'Quin, II
IPC分类号： G06F1100
CPC分类号： G06F11/2035 , G06F11/004 , G06F11/0724 , G06F11/076 , G06F11/079 , G06F11/2023 , G06F11/2028 , G06F2212/1032
摘要： A method and apparatus in a multiprocessor data processing system for managing a plurality of processors. Monitoring for recoverable errors in a set of processors is performed. Responsive to detecting a recoverable error for a processor in the set of processors, a determination is made as to whether the recoverable error indicates a trend towards an unrecoverable error. Responsive to a determination that the recoverable error indicates a trend towards an unrecoverable error, actions are initiated to stop the processor.
摘要翻译：一种用于管理多个处理器的多处理器数据处理系统中的方法和装置。执行一组处理器中的可恢复错误的监视。响应于检测处理器集合中的处理器的可恢复误差，确定可恢复误差是否表示朝向不可恢复误差的趋势。响应于确定可恢复错误指示出不可恢复的错误的趋势，启动动作以停止处理器。

2. 发明授权

US06233680B1 Method and system for boot-time deconfiguration of a processor in a symmetrical multi-processing system 失效
标题翻译：用于对称多处理系统中处理器引导时解体的方法和系统
公开(公告)号：US06233680B1
公开(公告)日：2001-05-15
申请号：US09165952
申请日：1998-10-02
申请人： Douglas Craig Bossen , Alongkorn Kitamorn , Charles Andrew McLaughlin
发明人： Douglas Craig Bossen , Alongkorn Kitamorn , Charles Andrew McLaughlin
IPC分类号： G06F15177
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/079 , G06F11/0793 , G06F15/177
摘要： A method and system for deconfiguring a CPU in a processing system is disclosed. In one aspect, a processing system is disclosed that comprises a central processing unit (CPU), and a memory coupled to the CPU. The error status register for capturing information concerning the status of the CPU. The processing system includes a service processor for gathering and analyzing status information from the CPU error register. The processing system also includes a nonvolatile device coupled to the service processor. The nonvolatile device includes a deconfiguration area. The deconfiguration area stores information concerning the status of the CPU from the service processor. The deconfiguration area also provides information for deconfiguring a CPU during a boot time of the processing system. Accordingly, through the present invention, CPU errors are detected during normal computer operations by error detection logic. This detection is utilized during any subsequent boot process by service processor firmware to deallocate the defective CPU. This is accomplished through the use of error status registers within the CPU and through the use of a deconfiguration area in the nonvolatile device which provides information directly to the service processor.
摘要翻译：公开了一种用于在处理系统中对CPU进行解配置的方法和系统。在一个方面，公开了一种包括中央处理单元（CPU）和耦合到CPU的存储器的处理系统。用于捕获有关CPU状态的信息的错误状态寄存器。处理系统包括用于从CPU错误寄存器收集和分析状态信息的服务处理器。处理系统还包括耦合到服务处理器的非易失性设备。非易失性器件包括解配置区域。解除配置区域从服务处理器存储关于CPU的状态的信息。解除配置区域还提供了在处理系统的引导时间期间对CPU进行解除配置的信息。因此，通过本发明，通过错误检测逻辑在通常的计算机操作期间检测到CPU错误。这种检测在服务处理器固件的任何后续启动过程中被利用以释放有缺陷的CPU。这是通过使用CPU内的错误状态寄存器并通过使用非易失性设备中的解配置区来实现的，该非配置区域直接向服务处理器提供信息。

3. 发明授权

US06243823B1 Method and system for boot-time deconfiguration of a memory in a processing system 失效
标题翻译：用于处理系统中存储器引导时解配置的方法和系统
公开(公告)号：US06243823B1
公开(公告)日：2001-06-05
申请号：US09165955
申请日：1998-10-02
申请人： Douglas Craig Bossen , Alongkorn Kitamorn , Charles Andrew McLaughlin
发明人： Douglas Craig Bossen , Alongkorn Kitamorn , Charles Andrew McLaughlin
IPC分类号： G06F15177
CPC分类号： G06F11/142
摘要： A method and system for deconfiguring software in a processing system is disclosed. In one aspect, a processing system comprises a central processing unit (CPU), and a memory coupled to the CPU. The memory includes a memory array and a memory controller for capturing information concerning the status of the memory array. The processing system includes a service processor for gathering and analyzing status information from the memory controller. The processing system also includes a nonvolatile device coupled to the CPU and the service processor. The nonvolatile device includes a deconfiguration area. The deconfiguration area stores information concerning the status of the memory array from the service processor. The deconfiguration area also provides information for deconfiguring at least a portion of the memory array during a boot time of the processing system. Accordingly, through the present invention, memory errors are detected during normal computer operations by error detection logic. This detection is utilized during any subsequent boot process by service processor and CPU boot firmware to deallocate the defective memory module. This is accomplished through the use of error status registers within the memory controller and through the use of a deconfiguration area in the nonvolatile device which provides information directly to the CPU boot firmware.
摘要翻译：公开了一种在处理系统中解除配置软件的方法和系统。在一个方面，处理系统包括中央处理单元（CPU）和耦合到CPU的存储器。存储器包括存储器阵列和用于捕获关于存储器阵列的状态的信息的存储器控制器。处理系统包括用于从存储器控制器收集和分析状态信息的服务处理器。处理系统还包括耦合到CPU和服务处理器的非易失性设备。非易失性器件包括解配置区域。解除配置区域从服务处理器存储关于存储器阵列的状态的信息。解配置区域还提供用于在处理系统的引导时间期间解除配置存储器阵列的至少一部分的信息。因此，通过本发明，通过错误检测逻辑在正常的计算机操作期间检测存储器错误。在任何后续引导过程中，服务处理器和CPU引导固件都会使用该检测来取消分配有缺陷的内存模块。这是通过使用存储器控制器内的错误状态寄存器并且通过使用非易失性设备中的解除配置区域来实现的，该非配置区域直接向CPU引导固件提供信息。

4. 发明授权

US06345369B1 Environmental and power error handling extension and analysis for systems with redundant components 有权
标题翻译：具有冗余组件的系统的环境和电源错误处理扩展和分析
公开(公告)号：US06345369B1
公开(公告)日：2002-02-05
申请号：US09190559
申请日：1998-11-12
申请人： Alongkorn Kitamorn , Charles Andrew McLaughlin , Kanisha Patel , Donald LeRoy Thorson
发明人： Alongkorn Kitamorn , Charles Andrew McLaughlin , Kanisha Patel , Donald LeRoy Thorson
IPC分类号： G06F1116
CPC分类号： G06F11/3058 , G06F11/2015 , G06F11/2268
摘要： Aspects for detecting environmental faults in redundant components of a computer system are described. In an exemplary method aspect, the method includes monitoring system environment conditions, including a status for redundant power supply and cooling components. The method further includes registering a failure condition with an appropriate error type when a monitored system environment condition exceeds a design threshold, and utilizing the registered failure condition as data in an architected error log.
摘要翻译：描述了用于检测计算机系统的冗余部件中的环境故障的方面。在示例性方法方面，该方法包括监视系统环境条件，包括冗余电源和冷却组件的状态。该方法还包括：当被监视的系统环境条件超过设计阈值时，使用适当的错误类型登记故障条件，并将登记的故障条件作为建筑错误日志中的数据。

5. 发明授权

US6119246A Error collection coordination for software-readable and non-software readable fault isolation registers in a computer system 失效
标题翻译：计算机系统中软件可读和非软件可读故障隔离寄存器的错误收集协调
公开(公告)号：US6119246A
公开(公告)日：2000-09-12
申请号：US829018
申请日：1997-03-31
申请人： Charles Andrew McLaughlin , Alongkorn Kitamorn , Sayileela Nulu
发明人： Charles Andrew McLaughlin , Alongkorn Kitamorn , Sayileela Nulu
IPC分类号： G06F11/00 , G06F11/273
CPC分类号： G06F11/2736 , G06F11/0775
摘要： The present invention provides method and system aspects for performing error data gathering from fault isolation registers of a computer system following a machine check occurrence. A method aspect includes utilizing firmware to perform failure information retrieval in software accessible registers and initiating a service processor (SP) for failure data retrieval in non-software accessible registers. The method further includes coordinating the combination of the failure information retrieved and the failure data retrieved in an error log for use in isolation of a fault source in the computer system.
摘要翻译：本发明提供了用于在机器检查发生之后从计算机系统的故障隔离寄存器执行错误数据采集的方法和系统方面。方法方面包括利用固件在软件可访问寄存器中执行故障信息检索，并启动用于非软件可访问寄存器中的故障数据检索的服务处理器（SP）。该方法还包括协调所检索的故障信息和在错误日志中检索的故障数据的组合，以用于隔离计算机系统中的故障源。

6. 发明授权

US5951686A Method and system for reboot recovery 失效
标题翻译：重新启动恢复的方法和系统
公开(公告)号：US5951686A
公开(公告)日：1999-09-14
申请号：US829089
申请日：1997-03-31
申请人： Charles Andrew McLaughlin , Alongkorn Kitamorn , Chet Mehta , John Steven Langford
发明人： Charles Andrew McLaughlin , Alongkorn Kitamorn , Chet Mehta , John Steven Langford
IPC分类号： G06F11/14 , G06F9/445
CPC分类号： G06F11/1417
摘要： A computer system with reboot capability includes a processing mechanism, the processing mechanism supporting an operating system. The system further includes a service processor coupled to the processing mechanism, the service processor determining whether a reboot operation is needed. In addition, the computer system includes a memory mechanism coupled to the processing mechanism and the service processor, the memory mechanism storing a plurality of platform policy parameters and an automatic restart policy of the operating system to support the reboot operation of the service processor.
摘要翻译：具有重启功能的计算机系统包括处理机构，支持操作系统的处理机构。该系统还包括耦合到处理机构的服务处理器，服务处理器确定是否需要重启操作。此外，计算机系统包括耦合到处理机构和服务处理器的存储器机构，存储机构存储多个平台策略参数和操作系统的自动重启策略，以支持服务处理器的重新启动操作。

7. 发明授权

US06502208B1 Method and system for check stop error handling 失效
标题翻译：检查停止错误处理的方法和系统
公开(公告)号：US06502208B1
公开(公告)日：2002-12-31
申请号：US08829017
申请日：1997-03-31
申请人： Charles Andrew McLaughlin , Alongkorn Kitamorn
发明人： Charles Andrew McLaughlin , Alongkorn Kitamorn
IPC分类号： H02H305
CPC分类号： G06F11/0772 , G06F11/0787 , G06F11/0793 , G06F11/1417
摘要： Method and system aspects for check stop error handling are provided. A method aspect for check stop error handling in a computer system, the computer system comprising a plurality of components including a processor that supports an operating system and firmware, includes utilizing a service processor following a check stop error for error data retrieval and attempting a reboot of the computer system. The method further includes initiating firmware for failure reporting based on the error data retrieval when the reboot is successful.
摘要翻译：提供了检查停止错误处理的方法和系统方面。一种用于计算机系统中的检查停止错误处理的方法方面，所述计算机系统包括多个组件，所述多个组件包括支持操作系统和固件的处理器，所述计算机系统包括利用检查停止错误后的服务处理器进行错误数据检索并尝试重新启动的计算机系统。该方法还包括当重新引导成功时基于错误数据检索启动用于故障报告的固件。

8. 发明授权

US06557121B1 Method and system for fault isolation for PCI bus errors 失效
标题翻译：使用递归分类的PCI总线错误故障隔离方法和系统
公开(公告)号：US06557121B1
公开(公告)日：2003-04-29
申请号：US08829088
申请日：1997-03-31
申请人： Charles Andrew McLaughlin , Alongkorn Kitamorn
发明人： Charles Andrew McLaughlin , Alongkorn Kitamorn
IPC分类号： G06F100
CPC分类号： G06F11/221 , G06F11/2205 , G06F11/2273
摘要： Method and system aspects for fault isolation on a bus are provided. In a method aspect, a method for isolating a fault condition on a bus of a computer system, the computer system including an input/output (I/O) subsystem formed by a plurality of I/O devices communicating via the bus, includes categorizing, in a recursive manner, the I/O subsystem, and isolating a source of an error condition within the I/O subsystem. Further, the I/O subsystem communicates via a peripheral component interconnect, PCI, bus. In a system aspect, a computer system for isolating a fault condition on a PCI bus includes a processing mechanism, and an input/output mechanism, coupled to the processing mechanism, comprising a plurality of input/output devices and bridges coupled to a PCI bus and communicating according to a PCI standard. In addition, the system includes a fault isolation mechanism within the processing mechanism for identifying a source of an error condition in the input/output mechanism. Further, the fault isolation mechanism performs categorization of the input/output mechanism in a recursive manner.
摘要翻译：提供了总线故障隔离的方法和系统方面。在方法方面，一种用于隔离计算机系统的总线上的故障状况的方法，所述计算机系统包括由经由所述总线通信的多个I / O设备形成的输入/输出（I / O）子系统，包括分类以递归的方式，I / O子系统，并隔离I / O子系统中的错误状况的源。此外，I / O子系统通过外围组件互连，PCI，总线进行通信。在系统方面，用于隔离PCI总线上的故障状况的计算机系统包括耦合到处理机构的处理机构和输入/输出机构，包括耦合到PCI总线的多个输入/输出设备和桥接器并根据PCI标准进行通信。另外，该系统包括处理机构内的用于识别输入/输出机构中的错误状况的源的故障隔离机构。此外，故障隔离机构以递归的方式进行输入输出机构的分类。

9. 发明授权

US06832329B2 Cache thresholding method, apparatus, and program for predictive reporting of array bit line or driver failures 失效
标题翻译：用于阵列位线或驱动器故障预测报告的缓存阈值法，装置和程序
公开(公告)号：US06832329B2
公开(公告)日：2004-12-14
申请号：US09779365
申请日：2001-02-08
申请人： George Henry Ahrens , Alongkorn Kitamorn , Charles Andrew McLaughlin , Michael Thomas Vaden
发明人： George Henry Ahrens , Alongkorn Kitamorn , Charles Andrew McLaughlin , Michael Thomas Vaden
IPC分类号： G06F1100
CPC分类号： G06F11/0751 , G06F11/076
摘要： A mechanism is provided for predicting cache array bit line or driver failures. This mechanism checks for five consecutive errors at different addresses within the same syndrome on invocation of event scan polling to characterize the failure. Once the failure is characterized, it is reported to the system for corrective maintenance including dynamic and/or boot time processor deconfiguration or preventive processor replacement.
摘要翻译：提供了一种用于预测高速缓存阵列位线或驱动器故障的机制。该机制在事件扫描轮询调用的同一综合征中检查不同地址上的五个连续错误，以表征故障。一旦故障被表征，就向系统报告纠正性维护，包括动态和/或引导时间处理器解除配置或预防处理器更换。

10. 发明授权

US06223299B1 Enhanced error handling for I/O load/store operations to a PCI device via bad parity or zero byte enables 失效
标题翻译：通过坏的奇偶校验或零字节使I / O加载/存储操作到PCI设备的增强的错误处理能够实现
公开(公告)号：US06223299B1
公开(公告)日：2001-04-24
申请号：US09072418
申请日：1998-05-04
申请人： Douglas Craig Bossen , Charles Andrew McLaughlin , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
发明人： Douglas Craig Bossen , Charles Andrew McLaughlin , Danny Marvin Neal , James Otto Nicholson , Steven Mark Thurber
IPC分类号： G06F1100
CPC分类号： G06F11/0772 , G06F11/0745 , G06F11/0793
摘要： Device selects lines from each I/O device are brought into a PCI host bridge individually so that the device number of a failing device may be logged in an error register when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity of zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.
摘要翻译：设备选择每个I / O设备的线路分别插入PCI主机桥，以便在PCI总线上出现错误时，可能会将故障设备的设备号记录在错误寄存器中。在错误寄存器复位之前，后续的加载和存储操作将被延迟，直到可以针对错误寄存器检查主体设备的设备编号。如果主机设备是先前发生故障的设备，则通过强制坏的奇偶校验或归零所有字节使能来防止对该设备的加载/存储操作完成。通过强制零字节的不良奇偶使能，I / O设备将通过激活其设备选择行来响应加载或存储请求，但不接受存储数据。允许对未登录在错误寄存器中的设备进行操作，正常情况下，正常情况下进行加载存储操作。因此，正常的系统操作不会受到影响，并且如果这种操作不会造成进一步的损坏，则允许错误恢复期间的操作进行。

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