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1. 发明授权

US10698859B2 Data multicasting with router replication and target instruction identification in a distributed multi-core processing architecture 有权
公开(公告)号：US10698859B2
公开(公告)日：2020-06-30
申请号：US12562940
申请日：2009-09-18
申请人： Doug Burger , Stephen W. Keckler , Dong Li
发明人： Doug Burger , Stephen W. Keckler , Dong Li
IPC分类号： G06F15/173 , G06F13/14 , G06F9/38 , H04L12/701
摘要： Methods, procedures, apparatuses, computer programs, computer-accessible mediums, processing arrangements and systems generally related to data multi-casting in a distributed processor architecture are described. Various implementations may include identifying a plurality of target instructions that are configured to receive a first message from a source; providing target routing instructions to the first message for each of the target instructions including selected information commonly shared by the target instructions; and, when two of the identified target instructions are located in different directions from one another relative to a router, replicating the first message and routing the replicated messages to each of the identified target instructions in the different directions. The providing target routing instructions may further comprise the selected information utilizing a subset of bits that is commonly shared by the target instructions and being identified as a left operand, right operand or predicate operand, and may include the selection of one of a plurality of multiple-instruction subsets of the target instructions.

2. 发明申请

US20110072239A1 DATA MULTICASTING IN A DISTRIBUTED PROCESSOR SYSTEM 审中-公开
标题翻译：分布式处理器系统中的数据采集
公开(公告)号：US20110072239A1
公开(公告)日：2011-03-24
申请号：US12562940
申请日：2009-09-18
申请人： Doug Burger , Stephen W. Keckler , Dong Li
发明人： Doug Burger , Stephen W. Keckler , Dong Li
IPC分类号： G06F15/76 , G06F9/02
摘要： Methods, procedures, apparatuses, computer programs, computer-accessible mediums, processing arrangements and systems generally related to data multi-casting in a distributed processor architecture are described. Various implementations may include identifying a plurality of target instructions that are configured to receive a first message from a source; providing target routing instructions to the first message for each of the target instructions including selected information commonly shared by the target instructions; and, when two of the identified target instructions are located in different directions from one another relative to a router, replicating the first message and routing the replicated messages to each of the identified target instructions in the different directions. The providing target routing instructions may further comprise the selected information utilizing a subset of bits that is commonly shared by the target instructions and being identified as a left operand, right operand or predicate operand, and may include the selection of one of a plurality of multiple-instruction subsets of the target instructions.
摘要翻译：描述了一般涉及分布式处理器架构中的数据多播的方法，程序，装置，计算机程序，计算机可访问介质，处理布置和系统。各种实现可以包括识别被配置为从源接收第一消息的多个目标指令; 为每个目标指令向第一消息提供目标路由指令，包括由目标指令共同共享的所选信息; 并且当所识别的目标指令中的两个相对于路由器彼此位于不同的方向时，复制第一消息并将复制的消息路由到不同方向上的所识别的目标指令中的每一个。提供目标路由指令还可以包括使用由目标指令共同共享并被识别为左操作数，右操作数或谓词操作数的位的子集的所选择的信息，并且可以包括选择多个多个 - 目标指令的指导子集。

3. 发明授权

US08127119B2 Control-flow prediction using multiple independent predictors 有权
标题翻译：使用多个独立预测因子的控制流预测
公开(公告)号：US08127119B2
公开(公告)日：2012-02-28
申请号：US12329517
申请日：2008-12-05
申请人： Doug Burger , Stephen W. Keckler , Nitya Ranganathan
发明人： Doug Burger , Stephen W. Keckler , Nitya Ranganathan
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/3848
摘要： The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods.
摘要翻译：本公开通常描述具有包括一个或多个分支预测器布置的多核处理器的计算系统。分支预测器被配置为预测与其相关联的并且将在计算系统的至少一个处理器核心上执行的单个和完整的程序指令流。通过描述的方法可以改善整体处理器性能和物理可扩展性。

4. 发明申请

US20100146209A1 METHOD AND APPARATUS FOR COMBINING INDEPENDENT DATA CACHES 审中-公开
标题翻译：用于组合独立数据缓存的方法和装置
公开(公告)号：US20100146209A1
公开(公告)日：2010-06-10
申请号：US12329530
申请日：2008-12-05
申请人： Doug Burger , Stephen W. Keckler , Changkyu Kim
发明人： Doug Burger , Stephen W. Keckler , Changkyu Kim
IPC分类号： G06F12/08
CPC分类号： G06F12/0851 , G06F12/0813 , G06F12/0815 , G06F2212/601 , Y02D10/13
摘要： Methods, apparatus, computer programs and systems related to combining independent data caches are described. Various implementations can dynamically aggregate multiple level-one (L1) data caches from distinct processors together, change the degree of interleaving (e.g., how much consecutive data is mapped to each participating data cache before addresses go on to the next one) among the cache banks, and retain the ability to subsequently adjust the number of data caches participating as one coherent cache, i.e., the degree of interleaving, such as when the requirements of an application or process change.
摘要翻译：描述了组合独立数据高速缓存的方法，装置，计算机程序和系统。各种实现可以将来自不同处理器的多个一级（L1）数据高速缓存动态地聚合在一起，改变交错的程度（例如，在地址进行到下一个之前，将多少连续的数据映射到每个参与数据高速缓存）并且保留随后调整作为一个一致高速缓存参与的数据高速缓存的数量的能力，即交织程度，例如当应用或过程的需求改变时。

5. 发明授权

US08433885B2 Method, system and computer-accessible medium for providing a distributed predicate prediction 有权
标题翻译：用于提供分布式谓词预测的方法，系统和计算机可访问介质
公开(公告)号：US08433885B2
公开(公告)日：2013-04-30
申请号：US12556440
申请日：2009-09-09
申请人： Doug Burger , Stephen W. Keckler , Hadi Esmaeilzadeh
发明人： Doug Burger , Stephen W. Keckler , Hadi Esmaeilzadeh
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F8/4451 , G06F9/3836 , G06F9/3842 , G06F9/3844
摘要： Examples of a system, method and computer accessible medium are provided to generate a predicate prediction for a distributed multi-core architecture. Using such system, method and computer accessible medium, it is possible to intelligently encode approximate predicate path information on branch instructions. Using this statically generated information, distributed predicate predictors can generate dynamic predicate histories that can facilitate an accurate prediction of high-confidence predicates, while minimizing the communication between the cores.
摘要翻译：提供系统，方法和计算机可访问介质的示例以生成分布式多核架构的谓词预测。使用这样的系统，方法和计算机可访问介质，可以智能地编码关于分支指令的近似谓词路径信息。使用这种静态生成的信息，分布式谓词预测器可以生成动态谓词历史，可以促进高信度谓词的准确预测，同时最小化内核之间的通信。

6. 发明申请

US20100325395A1 DEPENDENCE PREDICTION IN A MEMORY SYSTEM 审中-公开
标题翻译：记忆系统中的依赖性预测
公开(公告)号：US20100325395A1
公开(公告)日：2010-12-23
申请号：US12487804
申请日：2009-06-19
申请人： Doug Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
发明人： Doug Burger , Stephen W. Keckler , Robert McDonald , Lakshminarasimhan Sethumadhavan , Franziska Roesner
IPC分类号： G06F9/30
CPC分类号： G06F9/3834 , G06F9/3838
摘要： Techniques related to dependence prediction for a memory system are generally described. Various implementations may include a predictor storage storing a value corresponding to at least one prediction type associated with at least one load operation, and a state-machine having multiple states. For example, the state-machine may determine whether to execute the load operation based upon a prediction type associated with each of the states and a corresponding precedent to the load operation for the associated prediction type. The state-machine may further determine the prediction type for a subsequent load operation based on a result of the load operation. The states of the state machine may correspond to prediction types, which may be a conservative prediction type, an aggressive prediction type, or one or more N-store prediction types, for example.
摘要翻译：通常描述与存储器系统的依赖性预测相关的技术。各种实现可以包括存储对应于与至少一个加载操作相关联的至少一个预测类型的值的预测器存储器和具有多个状态的状态机。例如，状态机可以基于与每个状态相关联的预测类型以及相关联的预测类型的加载操作的相应先例来确定是否执行加载操作。状态机可以基于加载操作的结果进一步确定后续加载操作的预测类型。状态机的状态例如可以对应于预测类型，其可以是保守预测类型，积极预测类型或一个或多个N-存储预测类型。

7. 发明授权

US06965969B2 Non-uniform cache apparatus, systems, and methods 有权
标题翻译：非均匀缓存设备，系统和方法
公开(公告)号：US06965969B2
公开(公告)日：2005-11-15
申请号：US10962295
申请日：2004-10-08
申请人： Doug Burger , Stephen W. Keckler , Changkyu Kim
发明人： Doug Burger , Stephen W. Keckler , Changkyu Kim
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/12 , G06F2212/271
摘要： An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).
摘要翻译：装置或系统可以包括耦合到处理器的高速缓存控制电路和耦合到高速缓存控制电路的多个可独立存取的存储体（228）。一些银行可能会有不一致的延迟，组织成两个或更多的传播银行集（246）。方法可以包括访问存储体中的数据，其中所选择的存储体比其他存储体更靠近高速缓存控制电路和/或处理器，并且在确定第一数据是第一数据是第一数据时，将第一数据（445）从另一个存储体迁移到更靠近的存储体比第二基准更频繁地访问，第二基准可以迁移到另外的银行（451）。

8. 发明申请

US20100146249A1 Control-Flow Prediction Using Multiple Independent Predictors 有权
标题翻译：使用多个独立预测器的控制流预测
公开(公告)号：US20100146249A1
公开(公告)日：2010-06-10
申请号：US12329517
申请日：2008-12-05
申请人： Doug Burger , Stephen W. Keckler , Nitya Ranganathan
发明人： Doug Burger , Stephen W. Keckler , Nitya Ranganathan
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3848
摘要： The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods.
摘要翻译：本公开通常描述具有包括一个或多个分支预测器布置的多核处理器的计算系统。分支预测器被配置为预测与其相关联的并且将在计算系统的至少一个处理器核心上执行的单个和完整的程序指令流。通过描述的方法可以改善整体处理器性能和物理可扩展性。

9. 发明申请

US20130006739A1 ONLINE MARKETPLACE WITH SHIPPING INCENTIVES 有权
标题翻译：在线市场与运输激励
公开(公告)号：US20130006739A1
公开(公告)日：2013-01-03
申请号：US13174309
申请日：2011-06-30
申请人： Eric Horvitz , Gur Kimchi , Lili Cheng , Doug Burger , Stelios Paparizos , Marc Davis
发明人： Eric Horvitz , Gur Kimchi , Lili Cheng , Doug Burger , Stelios Paparizos , Marc Davis
IPC分类号： G06Q30/00
CPC分类号： G06Q30/0222 , G06Q10/0832 , G06Q10/08355 , G06Q30/06
摘要： A marketplace server and method for facilitating purchase transactions are provided. A marketplace server may include a routing engine configured to receive an order for goods from a first computing device associated with a first customer, with the order including a first delivery address of the customer. The routing engine also calculates a delivery route to the first delivery address. An offer engine is configured to create an offer for other goods. The offer includes a shipping incentive associated with a second delivery address of a second customer. The offer may be targeted to the second customer based on a proximity of the second delivery address to the delivery route. The offer engine sends the offer to a second computing device associated with the second customer. Upon receiving an acceptance of the offer from the computing device, the offer engine processes a purchase transaction for the offer.
摘要翻译：提供了一种用于促进采购交易的市场服务器和方法。市场服务器可以包括路由引擎，路由引擎被配置为从与第一客户相关联的第一计算设备接收货物的订单，该订单包括客户的第一传送地址。路由引擎还计算到第一个传送地址的传输路由。优惠引擎被配置为为其他商品创建报价。该优惠包括与第二客户的第二送货地址相关联的运送激励。基于第二递送地址与递送路线的接近度，该优惠可以针对第二客户。报价引擎将报价发送给与第二客户相关联的第二计算设备。在接收到来自计算设备的报价的接收之后，报价引擎处理该报价的购买交易。

10. 发明授权

US08201024B2 Managing memory faults 有权
标题翻译：管理内存故障
公开(公告)号：US08201024B2
公开(公告)日：2012-06-12
申请号：US12780931
申请日：2010-05-17
申请人： Doug Burger , James Larus , Karin Strauss , Jeremy Condit
发明人： Doug Burger , James Larus , Karin Strauss , Jeremy Condit
IPC分类号： G06F11/00
CPC分类号： G06F11/0766 , G06F11/073 , G06F11/0793
摘要： Embodiments are described for managing memory faults. An example system can include a memory controller module to manage memory cells and report memory faults. An error buffer module can store memory fault information received from the memory controller. A notification module can be in communication with the error buffer module. The notification module may generate a notification of a memory fault in a memory access operation. A system software module can provide services and manage executing programs on a processor. In addition, the system software module can receive the notifications of the memory fault for the memory access operation. A notification handler may be activated by an interrupt when the notification of the memory fault in the memory access operation is received.
摘要翻译：描述了用于管理存储器故障的实施例。示例系统可以包括用于管理存储器单元并报告存储器故障的存储器控制器模块。错误缓冲器模块可以存储从存储器控制器接收到的存储器故障信息。通知模块可以与错误缓冲模块通信。通知模块可以在存储器访问操作中生成存储器故障的通知。系统软件模块可以在处理器上提供服务和管理执行程序。此外，系统软件模块可以接收内存访问操作的内存故障通知。当接收到存储器访问操作中的存储器故障的通知时，通知处理程序可能被中断激活。

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