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1. 发明申请

US20100146209A1 METHOD AND APPARATUS FOR COMBINING INDEPENDENT DATA CACHES 审中-公开
标题翻译：用于组合独立数据缓存的方法和装置
公开(公告)号：US20100146209A1
公开(公告)日：2010-06-10
申请号：US12329530
申请日：2008-12-05
申请人： Doug Burger , Stephen W. Keckler , Changkyu Kim
发明人： Doug Burger , Stephen W. Keckler , Changkyu Kim
IPC分类号： G06F12/08
CPC分类号： G06F12/0851 , G06F12/0813 , G06F12/0815 , G06F2212/601 , Y02D10/13
摘要： Methods, apparatus, computer programs and systems related to combining independent data caches are described. Various implementations can dynamically aggregate multiple level-one (L1) data caches from distinct processors together, change the degree of interleaving (e.g., how much consecutive data is mapped to each participating data cache before addresses go on to the next one) among the cache banks, and retain the ability to subsequently adjust the number of data caches participating as one coherent cache, i.e., the degree of interleaving, such as when the requirements of an application or process change.
摘要翻译：描述了组合独立数据高速缓存的方法，装置，计算机程序和系统。各种实现可以将来自不同处理器的多个一级（L1）数据高速缓存动态地聚合在一起，改变交错的程度（例如，在地址进行到下一个之前，将多少连续的数据映射到每个参与数据高速缓存）并且保留随后调整作为一个一致高速缓存参与的数据高速缓存的数量的能力，即交织程度，例如当应用或过程的需求改变时。

2. 发明授权

US06965969B2 Non-uniform cache apparatus, systems, and methods 有权
标题翻译：非均匀缓存设备，系统和方法
公开(公告)号：US06965969B2
公开(公告)日：2005-11-15
申请号：US10962295
申请日：2004-10-08
申请人： Doug Burger , Stephen W. Keckler , Changkyu Kim
发明人： Doug Burger , Stephen W. Keckler , Changkyu Kim
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/12 , G06F2212/271
摘要： An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).
摘要翻译：装置或系统可以包括耦合到处理器的高速缓存控制电路和耦合到高速缓存控制电路的多个可独立存取的存储体（228）。一些银行可能会有不一致的延迟，组织成两个或更多的传播银行集（246）。方法可以包括访问存储体中的数据，其中所选择的存储体比其他存储体更靠近高速缓存控制电路和/或处理器，并且在确定第一数据是第一数据是第一数据时，将第一数据（445）从另一个存储体迁移到更靠近的存储体比第二基准更频繁地访问，第二基准可以迁移到另外的银行（451）。

3. 发明授权

US08180997B2 Dynamically composing processor cores to form logical processors 有权
标题翻译：动态组成处理器内核以形成逻辑处理器
公开(公告)号：US08180997B2
公开(公告)日：2012-05-15
申请号：US12166439
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
IPC分类号： G06F15/76
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3897 , G06F12/0875 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
摘要翻译：一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。通过动态分配处理器核来处理运行状态的变化，提高了性能和功率效率。

4. 发明申请

US20090013160A1 DYNAMICALLY COMPOSING PROCESSOR CORES TO FORM LOGICAL PROCESSORS 有权
标题翻译：将动态处理器与动态处理器动态组合
公开(公告)号：US20090013160A1
公开(公告)日：2009-01-08
申请号：US12166439
申请日：2008-07-02
申请人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
发明人： Douglas C. Burger , Stephen W. Keckler , Robert McDonald , Paul Gratz , Nitya Ranganathan , Lakshminarasimhan Sethumadhavan , Karthikevan Sankaralingam , Ramadass Nagarajan , Changkyu Kim , Haiming Liu
IPC分类号： G06F9/00 , G06F12/00
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3897 , G06F12/0875 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.
摘要翻译：一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。通过动态分配处理器核来处理运行状态的变化，提高了性能和功率效率。

5. 发明申请

US20050132140A1 Non-uniform cache apparatus, systems, and methods 有权
公开(公告)号：US20050132140A1
公开(公告)日：2005-06-16
申请号：US10962295
申请日：2004-10-08
申请人： Doug Burger , Stephen Keckler , Changkyu Kim
发明人： Doug Burger , Stephen Keckler , Changkyu Kim
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0897 , G06F12/0846 , G06F12/12 , G06F2212/271
摘要： An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).

6. 发明授权

US09153064B2 Grouping pixels to be textured 有权
标题翻译：将像素分组为纹理
公开(公告)号：US09153064B2
公开(公告)日：2015-10-06
申请号：US12646411
申请日：2009-12-23
申请人： Victor W. Lee , Ganesh S. Dasika , Mikhail Smelyanskiy , Jose Gonzalez , Changkyu Kim , Jatin Chhugani , Yen-Kuang Chen , Julio Gago , Santiago Galan , Victor Moya Del Barrio
发明人： Victor W. Lee , Ganesh S. Dasika , Mikhail Smelyanskiy , Jose Gonzalez , Changkyu Kim , Jatin Chhugani , Yen-Kuang Chen , Julio Gago , Santiago Galan , Victor Moya Del Barrio
IPC分类号： G06T15/00 , G06T15/04 , G06T11/00 , G06T7/60
CPC分类号： G06T15/04 , G06T7/60 , G06T11/001 , G06T15/005
摘要： A region or group of pixels may be textured as a unit, using a range specifier and one or more anchor pixels to define the group. In some embodiments, processing grouped pixels improves efficiency.
摘要翻译：可以使用范围说明符和一个或多个定位像素来定义区域或一组像素作为单元进行纹理化。在一些实施例中，处理分组的像素提高了效率。

7. 发明授权

US08667221B2 Detection of streaming data in cache 有权
标题翻译：检测缓存中的流数据
公开(公告)号：US08667221B2
公开(公告)日：2014-03-04
申请号：US12099502
申请日：2008-04-08
申请人： Changkyu Kim , Christopher J. Hughes , Yen-Kuang Chen
发明人： Changkyu Kim , Christopher J. Hughes , Yen-Kuang Chen
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/128
摘要： An apparatus to detect streaming data in memory is presented. In one embodiment the apparatus use reuse bits and S-bits status for cache lines wherein an S-bit status indicates the data in the cache line are potentially streaming data. To enhance the efficiency of a cache, different measures can be applied to make the streaming data become the next victim during a replacement.
摘要翻译：提出了一种在存储器中检测流数据的装置。在一个实施例中，装置对高速缓存行使用重用位和S位状态，其中S位状态指示高速缓存行中的数据是潜在的流数据。为了提高高速缓存的效率，可以采用不同的措施来使流数据成为替换期间的下一个受害者。

8. 发明申请

US20130339395A1 PARALLEL OPERATION ON B+ TREES 有权
标题翻译：平行操作在B + TREES
公开(公告)号：US20130339395A1
公开(公告)日：2013-12-19
申请号：US13996508
申请日：2011-08-29
申请人： Jason D. Sewall , Changkyu Kim , Jatin Chhugani , Nadathur Rajagopalan Satish
发明人： Jason D. Sewall , Changkyu Kim , Jatin Chhugani , Nadathur Rajagopalan Satish
IPC分类号： G06F17/30
CPC分类号： G06F17/30327 , G06F9/5005 , G06F2209/5018
摘要： Embodiments of techniques and systems for parallel processing of B+ trees are described. A parallel B+ tree processing module with partitioning and redistribution may include a set of threads executing a batch of B+ tree operations on a B+ tree in parallel. The batch of operations may be partitioned amongst the threads. Next, a search may be performed to determine which leaf nodes in the B+ tree are to be affected by which operations. Then, the threads may redistribute operations between each other such that multiple threads will not operate on the same leaf node. The threads may then perform B+ tree operations on the leaf nodes of the B+ tree in parallel. Subsequent modifications to nodes in the B+ may similarly be redistributed and performed in parallel as the threads work up the tree.
摘要翻译：描述了用于B +树的并行处理的技术和系统的实施例。具有分区和再分配的并行B +树处理模块可以包括一组在B +树上并行执行一批B +树操作的线程。该批操作可以在线程之间划分。接下来，可以执行搜索以确定B +树中的哪些叶节点将受哪些操作影响。然后，线程可以在彼此之间重新分配操作，使得多个线程将不在同一叶节点上操作。然后，线程可以并行地在B +树的叶节点上执行B +树操作。当线程处理树时，对B +中的节点的后续修改可以类似地重新分布并且并行执行。

9. 发明申请

US20120137074A1 METHOD AND APPARATUS FOR STREAM BUFFER MANAGEMENT INSTRUCTIONS 有权
标题翻译：流缓冲器管理指令的方法和装置
公开(公告)号：US20120137074A1
公开(公告)日：2012-05-31
申请号：US12955763
申请日：2010-11-29
申请人： Daehyun Kim , Changkyu Kim , Victor W. Lee , Jatin Chhugani , Nadathur Rajagopalan Satish
发明人： Daehyun Kim , Changkyu Kim , Victor W. Lee , Jatin Chhugani , Nadathur Rajagopalan Satish
IPC分类号： G06F12/08 , G06F12/02 , G06F12/16
CPC分类号： G06F12/0862 , G06F9/3004 , G06F2212/6022
摘要： A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy.
摘要翻译：一种在处理器中执行流缓冲器管理指令的方法和系统。在本发明的一个实施例中，流缓冲器管理指令有助于创建和使用处理器的专用存储空间或流缓冲器。专用存储器空间是连续存储器空间，并且在本发明的一个实施例中具有顺序或线性寻址方案。处理器具有执行流缓冲器管理指令的逻辑，以将来自源存储器地址的数据复制到用期望的存储器层级指定的目的地存储器地址。

10. 发明授权

US08171223B2 Method and system to increase concurrency and control replication in a multi-core cache hierarchy 有权
标题翻译：在多核缓存层次结构中增加并发性和控制复制的方法和系统
公开(公告)号：US08171223B2
公开(公告)日：2012-05-01
申请号：US12315442
申请日：2008-12-03
申请人： Christopher J. Hughes , Changkyu Kim , Yen-Kuang Chen
发明人： Christopher J. Hughes , Changkyu Kim , Yen-Kuang Chen
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A directory of a private cache hierarchy is provided to maintain coherency between data stored in the cache hierarchy, where the directory is to enable concurrent cache-to-cache transfer of data to two private caches from another private cache. This directory can be implemented in a system having a multi-core processor. Other embodiments are described.
摘要翻译：提供专用高速缓存层级的目录以维持存储在高速缓存层次结构中的数据之间的一致性，其中目录是启用数据的并发缓存到高速缓存传输到来自另一专用高速缓存的两个专用高速缓存。该目录可以在具有多核处理器的系统中实现。描述其他实施例。

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