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1. 发明申请

US20140008604A1 Super-Long Semiconductor Nano-Wire Structure and Method of Making 审中-公开
标题翻译：超长半导体纳米线结构及制作方法
公开(公告)号：US20140008604A1
公开(公告)日：2014-01-09
申请号：US13502110
申请日：2011-09-28
申请人： Dongping Wu , Shi-Li Zhang , Zhiwei Zhu , Wei Zhang
发明人： Dongping Wu , Shi-Li Zhang , Zhiwei Zhu , Wei Zhang
IPC分类号： H01L29/06 , H01L21/308
CPC分类号： H01L29/0669 , B82Y10/00 , B82Y40/00 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L29/122
摘要： The present invention disclosure provides a super-long semiconductor nanowire structure. The super-long semiconductor nanowire structure is intermittently widened to prevent fractures in the super-long semiconductor nanowire structure. At the same time, the present invention further provides a method of making a super-long semiconductor nanowire structure. The method forms an intermittently widened super-long semiconductor nanowire structure using photolithography and etching. Because the super-long semiconductor nanowire structure is intermittently widened, fracturing of the super-long semiconductor nanowire structure during etching can be avoided, making it easier to form a super-long and ultra-thin semiconductor nanowire structure.
摘要翻译：本发明公开了一种超长半导体纳米线结构。超长半导体纳米线结构被间歇地加宽以防止超长半导体纳米线结构中的断裂。同时，本发明还提供了制造超长半导体纳米线结构的方法。该方法使用光刻和蚀刻形成间歇加宽的超长半导体纳米线结构。因为超长半导体纳米线结构被间歇地加宽，所以可以避免在蚀刻过程中超长半导体纳米线结构的断裂，从而更容易形成超长和超薄的半导体纳米线结构。

2. 发明授权

US08697529B2 Schottky junction source/drain transistor and method of making 失效
标题翻译：肖特基结源极/漏极晶体管及其制造方法
公开(公告)号：US08697529B2
公开(公告)日：2014-04-15
申请号：US13508731
申请日：2011-09-28
申请人： Dongping Wu , Jun Luo , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Jun Luo , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L21/336 , H01L21/338
CPC分类号： H01L29/7839 , H01L29/6653 , H01L29/66848
摘要： A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth.
摘要翻译：一种制造晶体管的方法，包括：提供半导体衬底; 在所述半导体衬底上形成栅叠层; 在半导体衬底上形成绝缘层; 在绝缘层上形成耗尽层; 蚀刻耗尽层和绝缘层; 在所述半导体衬底上形成金属层; 进行热退火; 并去除金属层。作为本发明的优点，每个侧壁的上部外侧部分包括能够与金属层反应的材料，从而在退火过程中吸收侧壁两侧的金属，从而防止金属朝向半导体层，并且确保形成的肖特基结可以是超薄和均匀的，并且具有可控和抑制的横向生长。

3. 发明申请

US20140048875A1 Asymmetrical Gate MOS Device and Method of Making 有权
标题翻译：非对称门MOS器件及制作方法
公开(公告)号：US20140048875A1
公开(公告)日：2014-02-20
申请号：US14113705
申请日：2011-12-28
申请人： Dongping Wu , Cheng Hu , Lun Zhu , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Cheng Hu , Lun Zhu , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L21/28008 , H01L21/26586 , H01L21/28097 , H01L21/28105 , H01L21/2815 , H01L21/28518 , H01L29/04 , H01L29/4975 , H01L29/66575 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented.
摘要翻译：公开了一种非对称门MOS器件。栅极是金属栅极，金属栅极在源极侧与MOS器件的漏极侧具有不同的功函，使得MOS器件的整体性能参数更加优化。还公开了制造不对称栅极MOS器件的方法。在该方法中，将掺杂剂离子注入到MOS器件的栅极中，以使栅极在源极侧与MOS器件的漏极侧上具有不同的功函数。结果，MOS器件的整体性能参数更加优化。该方法可以很容易地实现。

4. 发明申请

US20140034955A1 Nano-MOS Devices and Method of Making 审中-公开
标题翻译：纳米MOS器件及其制造方法
公开(公告)号：US20140034955A1
公开(公告)日：2014-02-06
申请号：US13519315
申请日：2011-10-31
申请人： Dongping Wu , Cheng Hu , Luo Zhu , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Cheng Hu , Luo Zhu , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L21/285 , H01L29/04 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/41
CPC分类号： H01L21/28518 , H01L21/28097 , H01L21/2815 , H01L21/28255 , H01L21/28264 , H01L21/32053 , H01L29/04 , H01L29/413 , H01L29/41758 , H01L29/42376 , H01L29/4238 , H01L29/4975 , H01L29/66477 , H01L29/66575 , H01L29/78
摘要： The present invention discloses a method of making nano-MOS devices having a metal gate, thereby avoiding the poly depletion effect, and enhancing the MOS device's performance. The method forms metal gates by depositing a metal film over sidewall surfaces on two sides of a polycrystalline semiconductor layer. The metal in the metal film diffuses toward the sidewall surfaces of the polycrystalline semiconductor layer and forms, after annealing, metal-semiconductor compound nanowires (i.e., metal gates) on the sidewall surfaces of the polycrystalline semiconductor layer. Thus, high-resolution lithography is not required to form metal compound semiconductor nanowires, resulting in significant cost saving. At the same time, a nano-MOS device is also disclosed, which includes a metal gate, thereby avoiding the poly depletion effect, and resulting in enhanced MOS device performance.
摘要翻译：本发明公开了一种制造具有金属栅极的纳米MOS器件的方法，从而避免多晶硅耗尽效应，并提高MOS器件的性能。该方法通过在多晶半导体层的两侧上的侧壁表面上沉积金属膜来形成金属栅极。金属膜中的金属向多晶半导体层的侧壁表面扩散，并且在多晶半导体层的侧壁表面上退火后形成金属 - 半导体化合物纳米线（即，金属栅极）。因此，不需要高分辨率光刻来形成金属化合物半导体纳米线，导致显着的成本节省。同时，还公开了一种纳米MOS器件，其包括金属栅极，从而避免多晶硅耗尽效应，并且导致增强的MOS器件性能。

5. 发明申请

US20140008710A1 Metal/Semiconductor Compound Thin Film and a DRAM Storage Cell and Method of Making 审中-公开
标题翻译：金属/半导体复合薄膜和DRAM存储单元及其制造方法
公开(公告)号：US20140008710A1
公开(公告)日：2014-01-09
申请号：US13394303
申请日：2011-09-28
申请人： Dongping Wu , Shili Zhang , Zhiwei Zhu , Wei Zhang
发明人： Dongping Wu , Shili Zhang , Zhiwei Zhu , Wei Zhang
IPC分类号： H01L29/49 , H01L27/108
CPC分类号： H01L29/4933 , H01L21/28525 , H01L27/108 , H01L27/10844 , H01L27/10855 , H01L27/10873
摘要： A metal-semiconductor-compound thin film is disclosed, which is formed between a semiconductor layer and a polycrystalline semiconductor layer, the metal-semiconductor-compound thin film having a thickness of about 2˜5 nm, so as to improve a contact between the semiconductor layer and the polycrystalline semiconductor layer. A DRAM storage cell is also disclosed. A metal-semiconductor-compound thin film having a thickness of about 2-5 nm is added between a drain region of a MOS transistor and a polycrystalline semiconductor buffer layer in the DRAM storage cell, so as to enhance read/write speed of the transistor of the DRAM storage cell while preventing excessive increase in leakage current between the drain region and a semiconductor substrate. A method for making a DRAM storage cell is also disclosed. A DRAM storage cell made using the method has a metal-semiconductor-compound thin film, with a thickness controlled at about 2˜5 nm, formed between a drain region of its MOS transitor and a polycrystalline semiconductor buffer layer, so as to enhance the performance of the DRAM storage cell.
摘要翻译：公开了一种形成在半导体层和多晶半导体层之间的金属 - 半导体化合物薄膜，其厚度为约2〜5nm的金属 - 半导体 - 化合物薄膜，从而改善了半导体层以及多晶半导体层。还公开了DRAM存储单元。在DRAM存储单元中的MOS晶体管的漏极区域和多晶半导体缓冲层之间添加厚度约为2-5nm的金属半导体化合物薄膜，以提高晶体管的读/写速度的同时防止漏极区域和半导体衬底之间的漏电流的过度增加。还公开了一种用于制造DRAM存储单元的方法。使用该方法制造的DRAM存储单元具有形成在其MOS跨极的漏极区域和多晶半导体缓冲层之间的厚度控制在约2〜5nm的金属 - 半导体 - 化合物薄膜，以便增强 DRAM存储单元的性能。

6. 发明申请

US20130295732A1 METHOD FOR MAKING FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：制作场效应晶体管的方法
公开(公告)号：US20130295732A1
公开(公告)日：2013-11-07
申请号：US13390328
申请日：2011-09-28
申请人： Dongping Wu , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/26513 , H01L21/2658 , H01L21/324 , H01L29/517 , H01L29/6659
摘要： The present invention provides a method for making a field effect transistor, comprising of the following steps: providing a silicon substrate with a first type, forming a shallow trench by photolithography and etching processes, and forming silicon dioxide shallow trench isolations inside the shallow trench; forming by deposition a high-K gate dielectric layer and a metal gate electrode layer on the substrate and the shallow trench isolations; forming a gate structure by photolithography and etching processes; forming source/drain extension regions by ion implantation of dopants of a second type; depositing an insulating layer to form sidewalls tightly adhered to the sides of the gate; forming source/drain regions and PN junction interfaces between the source/drain region and the silicon substrate by ion implantation of dopants of the second type; and performing microwave annealing to activate implanted ions. The novel process of making a field effect transistor in the present invention can achieve impurity activation in the source/drain area at a low temperature and can reduce the influence of source/drain annealing on high-K gate dielectric and metal gate electrode.
摘要翻译：本发明提供一种制造场效应晶体管的方法，包括以下步骤：提供具有第一类型的硅衬底，通过光刻和蚀刻工艺形成浅沟槽，以及在浅沟槽内形成二氧化硅浅沟槽隔离; 通过在衬底上沉积高K栅介质层和金属栅电极层并形成浅沟槽隔离; 通过光刻和蚀刻工艺形成栅极结构; 通过第二类掺杂剂的离子注入形成源/漏扩展区; 沉积绝缘层以形成紧密地粘附到栅极侧面的侧壁; 通过第二类掺杂剂的离子注入在源极/漏极区域和硅衬底之间形成源极/漏极区域和PN结界面; 并进行微波退火以激活注入的离子。在本发明中制造场效应晶体管的新颖方法可以在低温下在源极/漏极区域实现杂质活化，并且可以减少源极/漏极退火对高K栅极电介质和金属栅电极的影响。

7. 发明授权

US09209029B2 Asymmetrical gate MOS device and method of making 有权
标题翻译：非对称栅MOS器件及其制作方法
公开(公告)号：US09209029B2
公开(公告)日：2015-12-08
申请号：US14113705
申请日：2011-12-28
申请人： Dongping Wu , Cheng Hu , Lun Zhu , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Cheng Hu , Lun Zhu , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L21/336 , H01L21/28 , H01L21/285 , H01L29/04 , H01L29/66 , H01L29/78 , H01L29/49 , H01L21/265
CPC分类号： H01L21/28008 , H01L21/26586 , H01L21/28097 , H01L21/28105 , H01L21/2815 , H01L21/28518 , H01L29/04 , H01L29/4975 , H01L29/66575 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented.
摘要翻译：公开了一种非对称门MOS器件。栅极是金属栅极，金属栅极在源极侧与MOS器件的漏极侧具有不同的功函，使得MOS器件的整体性能参数更加优化。还公开了制造不对称栅极MOS器件的方法。在该方法中，将掺杂剂离子注入到MOS器件的栅极中，以使栅极在源极侧与MOS器件的漏极侧上具有不同的功函数。结果，MOS器件的整体性能参数更加优化。该方法可以很容易地实现。

8. 发明申请

US20130270615A1 METHOD FOR MAKING TRANSISTORS 失效
标题翻译：制造晶体管的方法
公开(公告)号：US20130270615A1
公开(公告)日：2013-10-17
申请号：US13508731
申请日：2011-09-28
申请人： Dongping Wu , Jun Luo , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Jun Luo , Yinghua Piao , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7839 , H01L29/6653 , H01L29/66848
摘要： A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth.
摘要翻译：一种制造晶体管的方法，包括：提供半导体衬底; 在所述半导体衬底上形成栅叠层; 在半导体衬底上形成绝缘层; 在绝缘层上形成耗尽层; 蚀刻耗尽层和绝缘层; 在所述半导体衬底上形成金属层; 进行热退火; 并去除金属层。作为本发明的优点，每个侧壁的上部外侧部分包括能够与金属层反应的材料，从而在退火过程中吸收侧壁两侧的金属，从而防止金属朝向半导体层，并且确保形成的肖特基结可以是超薄和均匀的，并且具有可控和抑制的横向生长。

9. 发明申请

US20140034956A1 Asymmetric Gate MOS Device and Method of Making 审中-公开
标题翻译：不对称门MOS器件及其制造方法
公开(公告)号：US20140034956A1
公开(公告)日：2014-02-06
申请号：US13635071
申请日：2011-10-31
申请人： Dongping Wu , Cheng Hu , Lun Zhu , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Cheng Hu , Lun Zhu , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L21/285 , H01L21/28 , H01L29/04 , H01L29/78 , H01L29/66
CPC分类号： H01L21/28008 , H01L21/26586 , H01L21/28097 , H01L21/28105 , H01L21/2815 , H01L21/28518 , H01L29/04 , H01L29/4975 , H01L29/66575 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented.
摘要翻译：公开了一种不对称门MOS器件。栅极是金属栅极，金属栅极在源极侧与MOS器件的漏极侧具有不同的功函，使得MOS器件的整体性能参数更加优化。还公开了制造不对称栅极MOS器件的方法。在该方法中，将掺杂剂离子注入到MOS器件的栅极中，以使栅极在源极侧与MOS器件的漏极侧上具有不同的功函数。结果，MOS器件的整体性能参数更加优化。该方法可以很容易地实现。

10. 发明申请

US20140011355A1 Method of Making Metal/Semiconductor Compound Thin Film 审中-公开
标题翻译：制造金属/半导体复合薄膜的方法
公开(公告)号：US20140011355A1
公开(公告)日：2014-01-09
申请号：US13391623
申请日：2011-09-28
申请人： Dongping Wu , Zhiwei Zhu , Shili Zhang , Wei Zhang
发明人： Dongping Wu , Zhiwei Zhu , Shili Zhang , Wei Zhang
IPC分类号： H01L21/285
CPC分类号： H01L21/28518 , H01L21/2855 , H01L29/456
摘要： The present disclosure provides a method of making metal/semiconductor compound thin films, in which a target material is partially ionized into an ionic state during metal deposition using a PVD process, so as to produce metal ions, and in which a substrate bias voltage is applied to a semiconductor substrate, causing the metal ions to accelerate into the semiconductor substrate and enter the semiconductor substrate, resulting in more metal ions diffusing to the surface of the semiconductor substrate, greater deposition depth, and increased thickness of the eventually formed metal/semiconductor compound thin film. An amount of metal ions entering the semiconductor substrate can be adjusted by adjusting the substrate bias voltage, so as to adjust the thickness of the eventually formed metal/semiconductor compound.
摘要翻译：本公开提供了一种制造金属/半导体化合物薄膜的方法，其中使用PVD工艺在金属沉积期间目标材料被部分电离成离子状态，以产生金属离子，并且其中衬底偏压为施加到半导体衬底，使金属离子加速进入半导体衬底并进入半导体衬底，导致更多的金属离子扩散到半导体衬底的表面，更大的沉积深度和最终形成的金属/半导体的厚度增加复合薄膜。可以通过调整衬底偏置电压来调节进入半导体衬底的金属离子的量，以便调整最终形成的金属/半导体化合物的厚度。

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