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    • 7. 发明授权
    • Nonvolatile memory devices operable using negative bias voltages and related methods of operation
    • 可使用负偏置电压工作的非易失性存储器件和相关操作方法
    • US08248852B2
    • 2012-08-21
    • US12820628
    • 2010-06-22
    • Moosung KimYoungho Lim
    • Moosung KimYoungho Lim
    • G11C11/34
    • G11C16/10G11C16/34
    • A nonvolatile memory device includes a first address decoder and a second address decoder. The first address decoder includes a plurality of transistors disposed in a first well, and the second address decoder includes a plurality of transistors disposed in a second well that is electrically isolated from the first well. The first and second address decoders are associated with first and second memory blocks, respectively. A switch circuit is configured to provide a negative voltage to one of the first address decoder and the second address decoder on the basis of block address information that specifies an address included in one of the first memory block and the second memory block. Related methods of operation are also discussed.
    • 非易失性存储器件包括第一地址解码器和第二地址解码器。 第一地址解码器包括设置在第一阱中的多个晶体管,并且第二地址译码器包括设置在与第一阱电绝缘的第二阱中的多个晶体管。 第一和第二地址解码器分别与第一和第二存储器块相关联。 开关电路被配置为基于指定包括在第一存储器块和第二存储器块之一中的地址的块地址信息来向第一地址译码器和第二地址译码器之一提供负电压。 还讨论了相关的操作方法。
    • 8. 发明申请
    • NONVOLATILE MEMORY DEVICES OPERABLE USING NEGATIVE BIAS VOLTAGES AND RELATED METHODS OF OPERATION
    • 使用负偏差电压运行的非易失性存储器件及相关操作方法
    • US20110096602A1
    • 2011-04-28
    • US12820628
    • 2010-06-22
    • Moosung KimYoungho Lim
    • Moosung KimYoungho Lim
    • G11C16/04G11C16/06
    • G11C16/10G11C16/34
    • A nonvolatile memory device includes a first address decoder and a second address decoder. The first address decoder includes a plurality of transistors disposed in a first well, and the second address decoder includes a plurality of transistors disposed in a second well that is electrically isolated from the first well. The first and second address decoders are associated with first and second memory blocks, respectively. A switch circuit is configured to provide a negative voltage to one of the first address decoder and the second address decoder on the basis of block address information that specifies an address included in one of the first memory block and the second memory block. Related methods of operation are also discussed.
    • 非易失性存储器件包括第一地址解码器和第二地址解码器。 第一地址解码器包括设置在第一阱中的多个晶体管,并且第二地址译码器包括设置在与第一阱电绝缘的第二阱中的多个晶体管。 第一和第二地址解码器分别与第一和第二存储器块相关联。 开关电路被配置为基于指定包括在第一存储器块和第二存储器块之一中的地址的块地址信息来向第一地址译码器和第二地址译码器之一提供负电压。 还讨论了相关的操作方法。