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1. 发明授权

US08036043B2 Nonvolatile semiconductor device and memory system including the same 有权
标题翻译：非易失性半导体器件和包括其的存储器系统
公开(公告)号：US08036043B2
公开(公告)日：2011-10-11
申请号：US12480352
申请日：2009-06-08
申请人： Dong-Yean Oh , Woon-Kyung Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C16/0483 , G11C16/10 , H01L27/11551 , H01L27/11556
摘要： A nonvolatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines, each source lines corresponding to the bit lines and memory cell strings vertically formed between each pair of the bit lines and source lines. Multiple strings of memory cells can be stacked in the vertical direction, and adjacent memory cell strings may share bit line or source line.
摘要翻译：一种非易失性半导体存储器件，包括垂直阵列结构，其包括与位线相同方向布置的位线和源极线，每个源极线对应于在每对位线和源极之间垂直形成的位线和存储单元串线条。多个存储单元串可以在垂直方向堆叠，并且相邻的存储单元串可以共享位线或源极线。

2. 发明授权

US08654585B2 NAND flash memory device and method of making same 有权
标题翻译： NAND闪存器件及其制作方法
公开(公告)号：US08654585B2
公开(公告)日：2014-02-18
申请号：US13553242
申请日：2012-07-19
申请人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.
摘要翻译：集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

3. 发明申请

US20120281475A1 NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME 有权
标题翻译： NAND闪存存储器件及其制造方法
公开(公告)号：US20120281475A1
公开(公告)日：2012-11-08
申请号：US13553242
申请日：2012-07-19
申请人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.
摘要翻译：集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

4. 发明授权

US08243518B2 NAND flash memory device and method of making same 有权
标题翻译： NAND闪存器件及其制作方法
公开(公告)号：US08243518B2
公开(公告)日：2012-08-14
申请号：US12424135
申请日：2009-04-15
申请人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.
摘要翻译：集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

5. 发明授权

US07494871B2 Semiconductor memory devices and methods for forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US07494871B2
公开(公告)日：2009-02-24
申请号：US11647671
申请日：2006-12-29
申请人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
发明人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.
摘要翻译：半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。绝缘层覆盖选择晶体管和单元晶体管。位线在绝缘层中并且电连接到相应的选择晶体管。沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

6. 发明授权

US08456918B2 NAND flash memory device and method of operating same to reduce a difference between channel potentials therein 有权
标题翻译： NAND闪存器件及其操作方法以减少其中的沟道电位之间的差异
公开(公告)号：US08456918B2
公开(公告)日：2013-06-04
申请号：US12405826
申请日：2009-03-17
申请人： Dong-Yean Oh , Woon-Kyung Lee , Jai Hyuk Song , Chang-Sub Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee , Jai Hyuk Song , Chang-Sub Lee
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： An flash memory device includes a block of NAND cell units, each NAND cell unit in the block includes n memory cell transistors MC controlled by a plurality of n wordlines, and is connected in series between a string selection transistor SST connected to a bitline and a ground selection transistor GST. While a programming voltage Vpgm is applied to a selected wordline WL , a cutoff voltage Vss is applied to a nearby unselected wordline closer to the ground selection transistor GST to isolate a first local channel Ch1 from a second local channel Ch2. As the location i of the selected wordline WL increases close to the SST, the second channel potential Vch2 tends to increase excessively, causing errors. The excessive increase of Vch2 is prevented by modifying the voltages applied to string select lines (SSL) and/or to the bit lines (BL), or the pass voltages Vpass applied to the unselected wordlines (WL location i is equal or greater than a predetermined (stored) location number x. If incremental step pulse programming (ISPP) is implemented, the applied voltages are modified only if the ISPP loop count j is equal or greater than a predetermined (stored) critical loop number y.
摘要翻译：闪速存储器件包括一块NAND单元单元，该块中的每个NAND单元单元包括由多个n个字线控制的n个存储单元晶体管MC，并串联连接在连接到位线的串选择晶体管SST和接地选择晶体管GST。当编程电压Vpgm被施加到所选字线WL时，截止电压Vss被施加到靠近接地选择晶体管GST的附近未选字线，以将第一本地信道Ch1与第二本地信道Ch2隔离。当所选择的字线WL i的位置i增加到接近于SST时，第二通道电位Vch2会过度增加，导致错误。通过修改施加到串选择线（SSL）和/或位线（BL）的电压或施加到未选择字线（WL ），只有当所选择的字线WL i位置i等于或大于预定（存储的）位置号码x时。如果实现增量步进脉冲编程（ISPP），只有当ISPP循环计数j等于或大于预定（存储）的关键循环数y时，才施加电压。

7. 发明申请

US20100020617A1 NONVOLATILE SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非线性半导体器件和包括其的存储器系统
公开(公告)号：US20100020617A1
公开(公告)日：2010-01-28
申请号：US12480352
申请日：2009-06-08
申请人： Dong-Yean Oh , Woon-Kyung Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/3454 , G11C16/0483 , G11C16/10 , H01L27/11551 , H01L27/11556
摘要： A nonvolatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines, each source lines corresponding to the bit lines and memory cell strings vertically formed between each pair of the bit lines and source lines. Multiple strings of memory cells can be stacked in the vertical direction, and adjacent memory cell strings may share bit line or source line.
摘要翻译：一种非易失性半导体存储器件，包括垂直阵列结构，其包括与位线相同方向布置的位线和源极线，每个源极线对应于在每对位线和源极之间垂直形成的位线和存储单元串线条。多个存储单元串可以在垂直方向堆叠，并且相邻的存储单元串可以共享位线或源极线。

8. 发明申请

US20090287879A1 NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME 有权
标题翻译： NAND闪存存储器件及其制造方法
公开(公告)号：US20090287879A1
公开(公告)日：2009-11-19
申请号：US12424135
申请日：2009-04-15
申请人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
IPC分类号： G06F12/00 , G11C16/04 , G11C16/06 , G06F12/02
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.
摘要翻译：集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

9. 发明申请

US20080081413A1 Semiconductor memory devices and methods for forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20080081413A1
公开(公告)日：2008-04-03
申请号：US11647671
申请日：2006-12-29
申请人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
发明人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.
摘要翻译：半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。绝缘层覆盖选择晶体管和单元晶体管。位线在绝缘层中并且电连接到相应的选择晶体管。沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

10. 发明申请

US20130168800A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130168800A1
公开(公告)日：2013-07-04
申请号：US13717803
申请日：2012-12-18
申请人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
发明人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
IPC分类号： H01L29/06
CPC分类号： H01L29/0657 , H01L27/0207 , H01L27/1157 , H01L27/11582
摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.
摘要翻译：提供了包括设置在基板上的第一和第二隔离图案的半导体器件。交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

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