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1. 发明申请

US20070029628A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070029628A1
公开(公告)日：2007-02-08
申请号：US11497362
申请日：2006-08-02
申请人： Dong-Jo Kang , In-Sun Park , Dae-Joung Kim
发明人： Dong-Jo Kang , In-Sun Park , Dae-Joung Kim
IPC分类号： H01L29/94
CPC分类号： H01L21/823443 , H01L21/823418 , H01L29/66507 , H01L29/6659 , H01L29/66659 , H01L29/7833 , H01L29/7835
摘要： A semiconductor device includes a gate structure formed on a substrate. The gate structure includes an uppermost first metal silicide layer pattern having a first thickness. Spacers are formed on sidewalls of the gate structure. One or more impurity regions are formed in the substrate adjacent to at least one sidewall of the gate structure. A second metal silicide layer pattern, having a second thickness thinner than the first thickness, is formed on the one or more impurity regions.
摘要翻译：半导体器件包括形成在衬底上的栅极结构。栅极结构包括具有第一厚度的最上面的第一金属硅化物层图案。隔板形成在栅极结构的侧壁上。在与栅极结构的至少一个侧壁相邻的衬底中形成一个或多个杂质区。在一个或多个杂质区上形成具有比第一厚度薄的第二厚度的第二金属硅化物层图案。

2. 发明授权

US07479434B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07479434B2
公开(公告)日：2009-01-20
申请号：US11497362
申请日：2006-08-02
申请人： Dong-Jo Kang , In-Sun Park , Dae-Joung Kim
发明人： Dong-Jo Kang , In-Sun Park , Dae-Joung Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823443 , H01L21/823418 , H01L29/66507 , H01L29/6659 , H01L29/66659 , H01L29/7833 , H01L29/7835
摘要： A semiconductor device includes a gate structure formed on a substrate. The gate structure includes an uppermost first metal silicide layer pattern having a first thickness. Spacers are formed on sidewalls of the gate structure. One or more impurity regions are formed in the substrate adjacent to at least one sidewall of the gate structure. A second metal silicide layer pattern, having a second thickness thinner than the first thickness, is formed on the one or more impurity regions.
摘要翻译：半导体器件包括形成在衬底上的栅极结构。栅极结构包括具有第一厚度的最上面的第一金属硅化物层图案。隔板形成在栅极结构的侧壁上。在与栅极结构的至少一个侧壁相邻的衬底中形成一个或多个杂质区。在一个或多个杂质区上形成具有比第一厚度薄的第二厚度的第二金属硅化物层图案。

3. 发明授权

US08232638B2 Interconnection structure having oxygen trap pattern in semiconductor device 失效
标题翻译：在半导体器件中具有氧阱图案的互连结构
公开(公告)号：US08232638B2
公开(公告)日：2012-07-31
申请号：US12195315
申请日：2008-08-20
申请人： Young-Tae Ma , In-Sun Park , Dong-Jo Kang , Hyun-Seok Lim , Do-Hyung Kim
发明人： Young-Tae Ma , In-Sun Park , Dong-Jo Kang , Hyun-Seok Lim , Do-Hyung Kim
IPC分类号： B32B15/00
CPC分类号： H01L21/7685 , H01L21/76805 , H01L21/76814 , H01L21/76888 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , Y10T428/31678 , H01L2924/00
摘要： An interconnection structure having an oxygen trap pattern in a semiconductor device, and a method of fabricating the same are provided. The interconnection structure includes a lower interlayer insulating layer formed on a semiconductor substrate. A metal layer pattern and a capping layer pattern are sequentially stacked on the lower interlayer insulating layer. An oxygen trap pattern is disposed on the capping layer pattern and includes a conductive oxygen trap pattern.
摘要翻译：提供了一种在半导体器件中具有氧阱图案的互连结构及其制造方法。互连结构包括形成在半导体衬底上的下层间绝缘层。金属层图案和覆盖层图案依次层叠在下层间绝缘层上。氧气阱图案设置在覆盖层图案上并且包括导电氧阱图案。

4. 发明申请

US20090008623A1 Methods of fabricating nonvolatile memory device and a nonvolatile memory device 审中-公开
标题翻译：制造非易失性存储器件和非易失性存储器件的方法
公开(公告)号：US20090008623A1
公开(公告)日：2009-01-08
申请号：US12216004
申请日：2008-06-27
申请人： Hyun-Seok Lim , In-Sun Park , Gyu-Hwan Oh , Do-Hyung Kim , Shin-Jae Kang
发明人： Hyun-Seok Lim , In-Sun Park , Gyu-Hwan Oh , Do-Hyung Kim , Shin-Jae Kang
IPC分类号： H01L47/00 , H01L21/311
CPC分类号： H01L21/28518 , G11C13/0004 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675
摘要： Methods of fabricating a nonvolatile memory device using a resistance material and a nonvolatile memory device are provided. According to example embodiments, a method of fabricating a nonvolatile memory device may include forming at least one semiconductor pattern on a substrate, forming a metal layer on the at least one semiconductor pattern, forming a mixed-phase metal silicide layer, in which at least two phases coexist, by performing at least one heat treatment on the substrate so that the at least one semiconductor pattern may react with the metal layer, and exposing the substrate to an etching gas.
摘要翻译：提供使用电阻材料制造非易失性存储器件和非易失性存储器件的方法。根据示例性实施例，制造非易失性存储器件的方法可以包括在衬底上形成至少一个半导体图案，在至少一个半导体图案上形成金属层，形成混合相金属硅化物层，其中至少两相共存，通过在基板上进行至少一次热处理，使得至少一个半导体图案可与金属层反应，并使基板暴露于蚀刻气体。

5. 发明申请

US20080230373A1 METHODS OF FORMING A PHASE-CHANGE MATERIAL LAYER INCLUDING TELLURIUM AND METHODS OF MANUFACTURING A PHASE-CHANGE MEMORY DEVICE USING THE SAME 有权
标题翻译：形成相变材料层的方法及其制造方法使用该方法的相变存储器件
公开(公告)号：US20080230373A1
公开(公告)日：2008-09-25
申请号：US12051043
申请日：2008-03-19
申请人： Do-Hyung Kim , Shin-Jae Kang , In-Sun Park , Hyun-Seok Lim , Gyu-Hwan Oh
发明人： Do-Hyung Kim , Shin-Jae Kang , In-Sun Park , Hyun-Seok Lim , Gyu-Hwan Oh
IPC分类号： C23C14/34
CPC分类号： C23C14/3414 , C23C14/0623 , G11B7/2433 , G11B7/252 , G11B2007/24312 , G11B2007/24314 , G11B2007/24316 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： The present invention provides methods of forming a phase-change material layer including providing a substrate and a chalcogenide target including germanium (Ge), antimony (Sb) and tellurium (Te) at a temperature wherein tellurium is volatilized and antimony is not volatilized, and performing a sputtering process to form the phase-change material layer including a chalcogenide material on the substrate. Methods of manufacturing a phase-change memory device using the same are also provided.
摘要翻译：本发明提供了形成相变材料层的方法，包括在碲被挥发并且锑不挥发的温度下提供包括锗（Ge），锑（Sb）和碲（Te）的基板和硫族化物靶，以及进行溅射工艺以在衬底上形成包括硫族化物材料的相变材料层。还提供了制造使用其的相变存储器件的方法。

6. 发明授权

US07122468B2 Methods of fabricating integrated circuit conductive contact structures including grooves 有权
标题翻译：制造集成电路导电接触结构包括沟槽的方法
公开(公告)号：US07122468B2
公开(公告)日：2006-10-17
申请号：US11039562
申请日：2005-01-20
申请人： Ju-Cheol Shin , Hyeon-Deok Lee , Hong-Mi Park , In-Sun Park
发明人： Ju-Cheol Shin , Hyeon-Deok Lee , Hong-Mi Park , In-Sun Park
IPC分类号： H01L21/4763
CPC分类号： H01L27/10894 , H01L21/76877 , H01L23/5226 , H01L27/10817 , H01L27/10885 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a substrate and a first insulating layer on the substrate that includes a first hole including a floor and a sidewall. A first conductive contact extends conformally on the sidewall and floor to define a groove in the first hole. A second insulating layer is provided on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is provided in the second hole and in the groove. These integrated circuits are fabricated by forming a first insulating layer on a substrate that includes a first hole including a floor and a sidewall. A first conductive contact is conformally formed on the sidewall and floor to define a groove in the first hole. A second insulating layer is formed on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is formed in the second hole and in the groove.
摘要翻译：集成电路包括衬底和衬底上的第一绝缘层，其包括包括地板和侧壁的第一孔。第一导电接触件在侧壁和底板上保形地延伸以在第一孔中限定凹槽。第二绝缘层设置在第一绝缘层上，并且包括露出槽的第二孔。在第二孔和凹槽中设置第二导电接触。这些集成电路通过在基板上形成第一绝缘层来制造，所述第一绝缘层包括包括地板和侧壁的第一孔。第一导电接触共形地形成在侧壁和地板上以在第一孔中限定凹槽。第二绝缘层形成在第一绝缘层上，并且包括暴露槽的第二孔。在第二孔和槽中形成第二导电接触。

7. 发明申请

US20060113615A1 Methods of fabricating a semiconductor device having a barrier metal layer and devices formed thereby 失效
公开(公告)号：US20060113615A1
公开(公告)日：2006-06-01
申请号：US11284653
申请日：2005-11-22
申请人： Eung-Joon Lee , Hyun-Young Kim , In-Sun Park , Hyun-Deok Lee
发明人： Eung-Joon Lee , Hyun-Young Kim , In-Sun Park , Hyun-Deok Lee
IPC分类号： H01L21/8238 , H01L29/94
CPC分类号： H01L21/3003 , H01L21/28518 , H01L21/28556 , H01L29/665 , H01L29/78
摘要： A semiconductor device is formed by forming a gate region, including a gate oxide layer, and impurity diffusion regions on a semiconductor substrate, forming a barrier metal layer on the gate region and the impurity diffusion regions of the semiconductor substrate, forming a passivation layer at an interface between the semiconductor substrate and the gate oxide layer to remove defects of the gate oxide layer, and then performing a nitridation process to remove impurities from the semiconductor substrate.

8. 发明授权

US07005373B2 Method for forming a metal silicide layer in a semiconductor device 有权
标题翻译：在半导体器件中形成金属硅化物层的方法
公开(公告)号：US07005373B2
公开(公告)日：2006-02-28
申请号：US10790921
申请日：2004-03-02
申请人： Eung-Joon Lee , In-Sun Park , Kwan-Jong Roh
发明人： Eung-Joon Lee , In-Sun Park , Kwan-Jong Roh
IPC分类号： H01L21/4763
CPC分类号： H01L29/6653 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665
摘要： On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.
摘要翻译：在衬底的第一和第二区域上分别形成包括第一栅极和第一间隔物的第一栅极结构，以及包括第二栅电极和第二间隔物的第二栅极结构。将第一和第二间隔物移除到不同的深度，使得第一和第二栅极的侧部具有不同的暴露厚度。在包括第一和第二栅极结构的第一和第二区域上形成金属硅化物层。形成在第二栅电极上的金属硅化物层具有大于形成在第一栅电极上的金属硅化物层的第一厚度的第二厚度。所得N型和P型MOS晶体管的栅极结构中的间隔物被去除到不同的厚度，从而最小化栅极结构中的变形，并且还改善栅电极的电特性和热稳定性。

9. 发明授权

US06905960B2 Method of forming a contact in a semiconductor device 失效
标题翻译：在半导体器件中形成接触的方法
公开(公告)号：US06905960B2
公开(公告)日：2005-06-14
申请号：US10657140
申请日：2003-09-09
申请人： Hong-Mi Park , Jong-Sik Chun , Hyeon-Deok Lee , In-Sun Park , Jong-Myeong Lee , Ju-Cheol Shin
发明人： Hong-Mi Park , Jong-Sik Chun , Hyeon-Deok Lee , In-Sun Park , Jong-Myeong Lee , Ju-Cheol Shin
IPC分类号： H01L21/28 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/76843 , H01L21/76871
摘要： In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.
摘要翻译：在半导体器件中形成接触的方法中，在半导体衬底上形成绝缘层。然后，通过选择性地蚀刻绝缘层形成接触孔。阻挡金属层沉积在接触孔的侧表面和底表面上，并且在绝缘层的顶表面上沉积到均匀的厚度。在阻挡金属层上沉积抗氧化金属材料的润湿层。在润湿层上形成金属层，并填充接触孔，从而在半导体器件中形成接触。

10. 发明授权

US08889543B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08889543B2
公开(公告)日：2014-11-18
申请号：US13795807
申请日：2013-03-12
申请人： Jong-Min Baek , In-Sun Park , Jong-Myeong Lee , Jong-Won Hong , Hei-Seung Kim , Jung-Soo Yoon
发明人： Jong-Min Baek , In-Sun Park , Jong-Myeong Lee , Jong-Won Hong , Hei-Seung Kim , Jung-Soo Yoon
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/76804 , H01L21/76814 , H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76844 , H01L21/76885
摘要： A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.
摘要翻译：制造半导体器件的方法包括在衬底上形成开关器件。在具有开关装置的基板中形成下部结构。下导电层形成在下结构上。牺牲掩模图案形成在下导电层上。通过使用牺牲掩模图案作为蚀刻掩模蚀刻下导电层来形成下导电图案。在具有较低导电图案的基板上形成层间绝缘层。通过平坦化层间绝缘层直到牺牲掩模图案曝光来形成层间绝缘图案。通过去除暴露的牺牲掩模图案来形成露出下导电图案的开口。在开口中形成与下导电图案自对准的上导电图案。

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