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1. 发明申请

US20060094188A1 Methods of fabricating flash memory devices and flash memory devices fabricated thereby 有权
标题翻译：制造闪存器件和闪存器件的方法
公开(公告)号：US20060094188A1
公开(公告)日：2006-05-04
申请号：US11261820
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Dong-Hyun Kim
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Dong-Hyun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.
摘要翻译：提供了制造闪速存储器件的方法和由此制造的闪存器件。一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。在有源区上形成多个第一导电层图案。第一导电层图案在活性区域的长度方向上彼此间隔开。在半导体衬底和第一导电层图案上共形形成绝缘层。在绝缘层上形成第二导电层。图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

2. 发明授权

US07338849B2 Methods of fabricating flash memory devices and flash memory devices fabricated thereby 有权
标题翻译：制造闪存器件和闪存器件的方法
公开(公告)号：US07338849B2
公开(公告)日：2008-03-04
申请号：US11261820
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Dong-Hyun Kim
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Dong-Hyun Kim
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.
摘要翻译：提供了制造闪速存储器件的方法和由此制造的闪存器件。一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。在有源区上形成多个第一导电层图案。第一导电层图案在活性区域的长度方向上彼此间隔开。在半导体衬底和第一导电层图案上共形形成绝缘层。在绝缘层上形成第二导电层。图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

3. 发明申请

US20070231989A1 Methods of fabricating nonvolatile memory devices 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20070231989A1
公开(公告)日：2007-10-04
申请号：US11807544
申请日：2007-05-29
申请人： Seung-Pil Chung , Jong-Ho Park , Kyeong-Koo Chi , Dong-Hyun Kim
发明人： Seung-Pil Chung , Jong-Ho Park , Kyeong-Koo Chi , Dong-Hyun Kim
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115
摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.
摘要翻译：非易失性存储器件包括半导体衬底，器件隔离膜，隧道绝缘膜，多个浮置栅极，栅极间电介质膜和控制栅极图案。沟槽形成在衬底中，其间限定有效区域。器件隔离膜位于衬底中的沟槽中。隧道绝缘膜位于衬底的有源区上。多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。栅极间电介质膜延伸穿过浮栅和器件隔离膜。控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。

4. 发明授权

US07510934B2 Methods of fabricating nonvolatile memory devices 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07510934B2
公开(公告)日：2009-03-31
申请号：US11807544
申请日：2007-05-29
申请人： Seung-Pil Chung , Jong-Ho Park , Kyeong-Koo Chi , Dong-Hyun Kim
发明人： Seung-Pil Chung , Jong-Ho Park , Kyeong-Koo Chi , Dong-Hyun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.
摘要翻译：非易失性存储器件包括半导体衬底，器件隔离膜，隧道绝缘膜，多个浮置栅极，栅极间电介质膜和控制栅极图案。沟槽形成在衬底中，其间限定有效区域。器件隔离膜位于衬底中的沟槽中。隧道绝缘膜位于衬底的有源区上。多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。栅极间电介质膜延伸穿过浮栅和器件隔离膜。控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。

5. 发明授权

US07242054B2 Nonvolatile memory devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US07242054B2
公开(公告)日：2007-07-10
申请号：US11190314
申请日：2005-07-26
申请人： Seung-Pil Chung , Jong-Ho Park , Kyeong-Koo Chi , Dong-Hyun Kim
发明人： Seung-Pil Chung , Jong-Ho Park , Kyeong-Koo Chi , Dong-Hyun Kim
IPC分类号： H01L29/788 , H01L29/423
CPC分类号： H01L27/11521 , H01L27/115
摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.
摘要翻译：非易失性存储器件包括半导体衬底，器件隔离膜，隧道绝缘膜，多个浮置栅极，栅极间电介质膜和控制栅极图案。沟槽形成在衬底中，其间限定有效区域。器件隔离膜位于衬底中的沟槽中。隧道绝缘膜位于衬底的有源区上。多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。栅极间电介质膜延伸穿过浮栅和器件隔离膜。控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。

6. 发明申请

US20060027856A1 Nonvolatile memory devices and methods of fabricating the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20060027856A1
公开(公告)日：2006-02-09
申请号：US11190314
申请日：2005-07-26
申请人： Seung-Pil Chung , Jong-Ho Park , Kyeong-Koo Chi , Dong-Hyun Kim
发明人： Seung-Pil Chung , Jong-Ho Park , Kyeong-Koo Chi , Dong-Hyun Kim
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.
摘要翻译：非易失性存储器件包括半导体衬底，器件隔离膜，隧道绝缘膜，多个浮置栅极，栅极间电介质膜和控制栅极图案。沟槽形成在衬底中，其间限定有效区域。器件隔离膜位于衬底中的沟槽中。隧道绝缘膜位于衬底的有源区上。多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。栅极间电介质膜延伸穿过浮栅和器件隔离膜。控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。

7. 发明授权

US08530954B2 Non-volatile memory devices including first and second blocking layer patterns 有权
标题翻译：包括第一和第二阻挡层图案的非易失性存储器件
公开(公告)号：US08530954B2
公开(公告)日：2013-09-10
申请号：US12491529
申请日：2009-06-25
申请人： Dong-Hyun Kim , Chang-Jin Kang
发明人： Dong-Hyun Kim , Chang-Jin Kang
IPC分类号： H01L29/792
CPC分类号： H01L21/28282
摘要： Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.
摘要翻译：非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。栅电极位于第一阻挡层图案上。第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

8. 发明授权

US07564094B2 Non-volatile memory devices and methods of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07564094B2
公开(公告)日：2009-07-21
申请号：US12004985
申请日：2007-12-21
申请人： Dong-Hyun Kim , Chang-Jin Kang
发明人： Dong-Hyun Kim , Chang-Jin Kang
IPC分类号： H01L21/8238
CPC分类号： H01L21/28282
摘要： Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.
摘要翻译：非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。栅电极位于第一阻挡层图案上。第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

9. 发明申请

US20080199975A1 METHODS OF FORMING A METAL OXIDE LAYER PATTERN HAVING A DECREASED LINE WIDTH OF A PORTION THEREOF AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：形成具有其部分的下降线宽度的金属氧化物层图案的方法和使用其制造半导体器件的方法
公开(公告)号：US20080199975A1
公开(公告)日：2008-08-21
申请号：US12032018
申请日：2008-02-15
申请人： Min-Joon Park , Chang-Jin Kang , Dong-Hyun Kim
发明人： Min-Joon Park , Chang-Jin Kang , Dong-Hyun Kim
IPC分类号： H01L21/18 , H01L21/3065
CPC分类号： H01L27/11521 , H01L21/0206 , H01L21/31116 , H01L21/31122 , H01L21/32136 , H01L27/115 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L29/40117
摘要： Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increases in a vertically downward direction; and etching the preliminary metal oxide layer pattern to form a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer. The present invention also provides methods of manufacturing a semiconductor device including forming a metal oxide layer and a first conductive layer on a substrate; etching the metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increase in a vertically downward direction; etching the first conductive layer to provide a first conductive layer pattern; and etching the preliminary metal oxide layer pattern to provide a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer pattern.
摘要翻译：本文提供了在衬底上形成金属氧化物层图案的方法，包括在衬底上提供初步金属氧化物层; 蚀刻初始金属氧化物层以提供初步金属氧化物层图案，其中预备金属氧化物层图案的线宽在垂直向下的方向上逐渐增加; 并且以使得预备金属氧化物层的下部的线宽减小的方式蚀刻初步金属氧化物层图案以形成金属氧化物层图案。本发明还提供了制造半导体器件的方法，包括在衬底上形成金属氧化物层和第一导电层; 蚀刻金属氧化物层以提供初步金属氧化物层图案，其中初始金属氧化物层图案的线宽在垂直向下的方向上逐渐增加; 蚀刻第一导电层以提供第一导电层图案; 并且蚀刻初步金属氧化物层图案以提供金属氧化物层图案，以便减小初步金属氧化物层图案的下部的线宽度。

10. 发明申请

US20080150008A1 Non-volatile memory devices and methods of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080150008A1
公开(公告)日：2008-06-26
申请号：US12004985
申请日：2007-12-21
申请人： Dong-Hyun Kim , Chang-Jin Kang
发明人： Dong-Hyun Kim , Chang-Jin Kang
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L21/28282
摘要： Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.
摘要翻译：非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。栅电极位于第一阻挡层图案上。第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

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