会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Apparatus and method for performing rounding and addition in parallel in floating point multiplier
    • 用于在浮点乘法器中并行执行舍入和加法的装置和方法
    • US06269385B1
    • 2001-07-31
    • US09126441
    • 1998-07-30
    • Tack Don HanWoo Chan Park
    • Tack Don HanWoo Chan Park
    • G06F738
    • G06F7/4876G06F7/49957
    • An apparatus and a method for performing rounding and addition in parallel in a floating point multiplier are disclosed, in which operation time and the size of a chip can be reduced. The apparatus includes an adder having an n bit half adder and an 1 bit full adder to add high n+1 bit from carry C and sum S of 2n bit and 1 bit of predictor, a Cinn−2 generator for generating carry Cinn−2 for addition of low n−2 bit to carry C and sum S of 2n bit, a predictor for providing 0 or 1 to the full adder when generating the added carry C of n bit and sum S of n+1 bit, a carry select adder for adding 0 or 1 to high n bit value of carry and sum added through the adder to output its result values i0 and i1, a selector for outputting a control signal of 0 or 1 to select a value obtained by addition and rounding from two output values of the carry select adder, a multiplexer for multiplexing the results of i0 and i1 from one of a round-to-nearest mode, a round-to-zero mode, and a round-to-infinity mode in response to the control signal of the selector, and a qNS0 logic circuit for generating the least significant bit LSB for a round value during no shift (NS). The floating point multiplier supports four rounding modes according to IEEE's standard.
    • 公开了一种用于在浮点乘法器中并行执行舍入和加法的装置和方法,其中可以减少操作时间和芯片的尺寸。 该装置包括具有n位半加法器和1位全加器的加法器,用于从进位C加上高n + 1位,并将2n位和1位预测器的和S相加,用于产生进位Cinn-2的Cinn-2发生器 为了加载低n-2位来携带C和2n位的和S,预测器在产生n位的相加进位C和n + 1位的和S时向全加器提供0或1,进位选择 加法器,用于将0或1加到通过加法器相加的进位和加法的高n位值,以输出其结果值i0和i1;输出0或1的控制信号的选择器,以选择通过加法和舍入从2获得的值 进位选择加法器的输出值,用于响应于该控制将多路复用从循环到最近模式,圆到零模式和圆到无限模式之一的i0和i1的结果的多路复用器 信号,以及qNS0逻辑电路,用于在无移位(NS)期间产生一个回合值的最低有效位LSB。 浮点乘法器根据IEEE标准支持四种四舍五入模式。
    • 5. 发明授权
    • Ray tracing core and method for processing ray tracing
    • 光线跟踪核心和处理光线跟踪的方法
    • US08836702B2
    • 2014-09-16
    • US13985125
    • 2011-02-18
    • Hyung Min YoonWoo Chan Park
    • Hyung Min YoonWoo Chan Park
    • G06T15/30G06T15/06
    • G06T15/06G06T2200/28
    • A ray tracing core comprises a ray tracing unit (RTU), a control unit, and a tree build unit (TBU). The ray tracing unit performs ray tracing based on a spatial partitioning structure. The control unit calculates the degree of complexity of the spatial partitioning structure by monitoring the load state of the ray tracing unit. The tree build unit builds the spatial partitioning structure having the degree of complexity which is calculated. The load state is determined based on a frame rate which is processed in the pertinent unit. The spatial partitioning structure applies a K-dimensional tree. For example, the degree of complexity can be modified according to either the maximum primitive number of a leaf node with respect to a K-dimensional tree structure or a tree depth.
    • 光线跟踪核心包括光线跟踪单元(RTU),控制单元和树构建单元(TBU)。 光线跟踪单元基于空间分割结构执行光线跟踪。 控制单元通过监视光线跟踪单元的负载状态来计算空间分割结构的复杂程度。 树构建单元构建具有计算复杂程度的空间分区结构。 基于在相关单元中处理的帧速率来确定负载状态。 空间分割结构应用K维树。 例如,可以根据相对于K维树结构或树深度的叶节点的最大原始数来修改复杂度。
    • 6. 发明授权
    • Apparatus and method of performing addition and rounding operation in parallel for floating-point arithmetic logical unit
    • 对浮点运算逻辑单元进行并行执行加法运算的装置和方法
    • US06785701B2
    • 2004-08-31
    • US09841708
    • 2001-04-23
    • Woo Chan ParkTack Don Han
    • Woo Chan ParkTack Don Han
    • G06F738
    • G06F7/485G06F7/49957G06F2207/3884
    • A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.
    • 在同时舍入方法(SRM)型浮点加法器中并行执行IEEE舍入和相加的浮点ALU。 浮点ALU包括用于旁路或反转第一分数部分和第二分数部分的对准/归一化部分,通过执行从指数部分获得的值或通过左侧执行归一化执行右移,执行对准 通过计算相对于第一分数部分的前导零,并获得保护位(G),圆比特(R)和粘性比特(Sy); 以及相对于通过对准/归一化部输出的第一分数部分和第二分数部分进行加法和舍入的加法和舍入操作部分。 根据浮点ALU,可以减少处理时间和硬件尺寸,可以直接使用SRM的硬件。
    • 7. 发明授权
    • 3D graphic accelerator and method for processing graphic acceleration using the same
    • 3D图形加速器和使用它的图形加速处理方法
    • US06570565B1
    • 2003-05-27
    • US09630650
    • 2000-08-02
    • Woo Chan ParkTack Don Han
    • Woo Chan ParkTack Don Han
    • G06T1540
    • G06T15/005G06T15/40
    • A 3D graphic accelerator and a method for processing a graphic acceleration using the same is provided in which the inputted primitives are geometrically processed, and existence of any transparent primitives or dominance/rarity of opaque primitives is determined among the geometrically processed primitives. The primitives are rendered in an object-order style and an image-order style in accordance with the determination. The information on the rendered primitives is stored in a corresponding frame buffer and a bucket, and the rendered primitives are display-refreshed. Thus, the 3D graphic accelerator with order- independent transparency and high performance is obtained.
    • 提供了3D图形加速器和使用其的图形加速处理方法,其中输入的图元被几何处理,并且在几何处理的图元中确定了不透明图元的任何透明图元或优势/稀有性的存在。 根据确定,原语以对象顺序样式和图像顺序样式呈现。 关于渲染的图元的信息存储在相应的帧缓冲器和桶中,并且渲染的图元被显示刷新。 因此,获得了具有独立于订单的透明度和高性能的3D图形加速器。