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    • 3. 发明授权
    • Ray tracing core and method for processing ray tracing
    • 光线跟踪核心和处理光线跟踪的方法
    • US08836702B2
    • 2014-09-16
    • US13985125
    • 2011-02-18
    • Hyung Min YoonWoo Chan Park
    • Hyung Min YoonWoo Chan Park
    • G06T15/30G06T15/06
    • G06T15/06G06T2200/28
    • A ray tracing core comprises a ray tracing unit (RTU), a control unit, and a tree build unit (TBU). The ray tracing unit performs ray tracing based on a spatial partitioning structure. The control unit calculates the degree of complexity of the spatial partitioning structure by monitoring the load state of the ray tracing unit. The tree build unit builds the spatial partitioning structure having the degree of complexity which is calculated. The load state is determined based on a frame rate which is processed in the pertinent unit. The spatial partitioning structure applies a K-dimensional tree. For example, the degree of complexity can be modified according to either the maximum primitive number of a leaf node with respect to a K-dimensional tree structure or a tree depth.
    • 光线跟踪核心包括光线跟踪单元(RTU),控制单元和树构建单元(TBU)。 光线跟踪单元基于空间分割结构执行光线跟踪。 控制单元通过监视光线跟踪单元的负载状态来计算空间分割结构的复杂程度。 树构建单元构建具有计算复杂程度的空间分区结构。 基于在相关单元中处理的帧速率来确定负载状态。 空间分割结构应用K维树。 例如,可以根据相对于K维树结构或树深度的叶节点的最大原始数来修改复杂度。
    • 6. 发明授权
    • Pixel cache, 3D graphics accelerator using the same, and method therefor
    • 像素缓存,3D图形加速器使用相同,及其方法
    • US07042462B2
    • 2006-05-09
    • US10731434
    • 2003-12-10
    • Jae-hyun KimYong-je KimTack-don HanWoo-chan ParkGil-hwan LeeIl-san Kim
    • Jae-hyun KimYong-je KimTack-don HanWoo-chan ParkGil-hwan LeeIl-san Kim
    • G09G5/36G06T15/40
    • G06T15/005G06T15/405
    • An effective structure of a pixel cache for use in a three-dimensional (3D) graphics accelerator is provided. The pixel cache includes a z-data storage unit that reads z-data from a frame memory and provides the read z-data to a pixel rasterization pipeline; and a color data storage unit that in advance reads and stores color data from the frame memory at the same time when the z-data storage unit reads the z-data from the frame memory, and provides the color data to the pixel rasterization pipeline only when the result of predetermined z-test is determined to be a success in the pixel rasterization pipeline. Accordingly, the pixel cache structure enables only color data required to be read and stored in advance before processing of the color data, thereby preventing access latency, increasing the efficiency of a color cache, and reducing power consumption.
    • 提供了用于三维(3D)图形加速器的像素高速缓存的有效结构。 像素高速缓存包括z数据存储单元,其从帧存储器读取z数据,并将读取的z数据提供给像素光栅化管线; 以及彩色数据存储单元,其在z数据存储单元从帧存储器读取z数据的同时,预先从帧存储器读取和存储颜色数据,并且仅将颜色数据提供给像素光栅化管线 当预定的z检验的结果被确定为在像素光栅化管线中成功时。 因此,在处理彩色数据之前,像素高速缓存结构仅能够预先读取和存储需要的颜色数据,从而防止访问等待时间,提高彩色高速缓存的效率,并降低功耗。
    • 7. 发明授权
    • Apparatus and method of performing addition and rounding operation in parallel for floating-point arithmetic logical unit
    • 对浮点运算逻辑单元进行并行执行加法运算的装置和方法
    • US06785701B2
    • 2004-08-31
    • US09841708
    • 2001-04-23
    • Woo Chan ParkTack Don Han
    • Woo Chan ParkTack Don Han
    • G06F738
    • G06F7/485G06F7/49957G06F2207/3884
    • A floating-point ALU that performs an IEEE rounding and an addition in parallel in a simultaneous rounding method (SRM) type floating-point adder. The floating-point ALU includes an alignment/normalization section for bypassing or inverting a first fraction part and a second fraction part, performing an alignment by performing a right shift as much as a value obtained from an exponent part or performing a normalization through a left shift by calculating a leading zero with respect to the first fraction part, and obtaining a guard bit (G), round bit (R), and sticky bit (Sy); and an addition and rounding operation section for performing a addition and rounding with respect to the first fraction part and second fraction part outputted through the alignment/normalization section. According to the floating-point ALU, the processing time and the hardware size can be reduced, and the hardware of the SRM can be used as it is.
    • 在同时舍入方法(SRM)型浮点加法器中并行执行IEEE舍入和相加的浮点ALU。 浮点ALU包括用于旁路或反转第一分数部分和第二分数部分的对准/归一化部分,通过执行从指数部分获得的值或通过左侧执行归一化执行右移,执行对准 通过计算相对于第一分数部分的前导零,并获得保护位(G),圆比特(R)和粘性比特(Sy); 以及相对于通过对准/归一化部输出的第一分数部分和第二分数部分进行加法和舍入的加法和舍入操作部分。 根据浮点ALU,可以减少处理时间和硬件尺寸,可以直接使用SRM的硬件。
    • 8. 发明授权
    • 3D graphic accelerator and method for processing graphic acceleration using the same
    • 3D图形加速器和使用它的图形加速处理方法
    • US06570565B1
    • 2003-05-27
    • US09630650
    • 2000-08-02
    • Woo Chan ParkTack Don Han
    • Woo Chan ParkTack Don Han
    • G06T1540
    • G06T15/005G06T15/40
    • A 3D graphic accelerator and a method for processing a graphic acceleration using the same is provided in which the inputted primitives are geometrically processed, and existence of any transparent primitives or dominance/rarity of opaque primitives is determined among the geometrically processed primitives. The primitives are rendered in an object-order style and an image-order style in accordance with the determination. The information on the rendered primitives is stored in a corresponding frame buffer and a bucket, and the rendered primitives are display-refreshed. Thus, the 3D graphic accelerator with order- independent transparency and high performance is obtained.
    • 提供了3D图形加速器和使用其的图形加速处理方法,其中输入的图元被几何处理,并且在几何处理的图元中确定了不透明图元的任何透明图元或优势/稀有性的存在。 根据确定,原语以对象顺序样式和图像顺序样式呈现。 关于渲染的图元的信息存储在相应的帧缓冲器和桶中,并且渲染的图元被显示刷新。 因此,获得了具有独立于订单的透明度和高性能的3D图形加速器。