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1. 发明授权

US09076542B2 Memory system having variable operating voltage and related method of operation 有权
标题翻译：具有可变工作电压和相关操作方法的存储器系统
公开(公告)号：US09076542B2
公开(公告)日：2015-07-07
申请号：US14077274
申请日：2013-11-12
申请人： Dong Hyun Sohn , Chan Kyung Kim , Yun Sang Lee
发明人： Dong Hyun Sohn , Chan Kyung Kim , Yun Sang Lee
IPC分类号： G11C11/00 , G11C11/14 , G11C11/36 , G11C11/16
CPC分类号： G11C11/1697 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A magneto-resistive random access memory (MRAM) including an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit including a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.
摘要翻译：包括具有MRAM单元的MRAM单元阵列的磁阻随机存取存储器（MRAM）以及被配置为产生MRAM单元的反向偏置电压的控制和电压产生单元。所述控制和电压产生单元包括命令解码器，其被配置为响应于从存储器控制器输出的命令产生解码信号;以及电压控制器和发生器，其被配置为基于所述解码信号产生具有幅度的所述反向偏置电压，以及从存储器控制器输出的复位信号。

2. 发明授权

US07501870B2 Duty cycle correction circuit and duty cycle correction method 有权
标题翻译：占空比校正电路和占空比校正方法
公开(公告)号：US07501870B2
公开(公告)日：2009-03-10
申请号：US11819414
申请日：2007-06-27
申请人： Hyun Su Choi , Chan Kyung Kim
发明人： Hyun Su Choi , Chan Kyung Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K5/133
摘要： A duty cycle correction circuit may include an error corrector adapted to correct duty cycles of first differential analog clock signals input to a pair of input terminals based on duty cycle correction signals input to a pair of control terminals and to output second differential analog clock signals having corrected duty cycles through a pair of output terminals, an analog to digital buffer adapted to convert the second differential analog clock signals to differential digital clock signals, a duty error detector adapted to detect duty cycles of the differential digital clock signals and to output a N bit digital signal, and a duty error correction signal generator adapted to output differential control current signals having current gains controlled based on the second differential analog clock signals and the N bit digital signal to the pair of control terminals as the duty cycle correction signals.
摘要翻译：占空比校正电路可以包括误差校正器，其适于基于输入到一对控制端子的占空比校正信号来校正输入到一对输入端子的第一差分模拟时钟信号的占空比，并输出具有通过一对输出端子，适于将第二差分模拟时钟信号转换为差分数字时钟信号的模数转换器的校正占空比;适用于检测差分数字时钟信号的占空比并输出N 以及负载误差校正信号发生器，其适于将具有基于第二差分模拟时钟信号和N位数字信号控制的电流增益的差分控制电流信号输出到该对控制端子，作为占空比校正信号。

3. 发明授权

US10090035B2 Semiconductor devices having separate source line structure 有权
公开(公告)号：US10090035B2
公开(公告)日：2018-10-02
申请号：US15388419
申请日：2016-12-22
申请人： Chan Kyung Kim
发明人： Chan Kyung Kim
IPC分类号： G11C7/06 , G11C7/10 , G11C11/16
摘要： A semiconductor device includes a bit-line sense amplifier (S/A) circuit configured to sense and amplify data stored in a resistive memory cell according to a reference current. The bit-line S/A circuit includes a cross-coupled latch circuit and a write latch circuit. The cross-coupled latch circuit is coupled to an input/output circuit via a first line and a complementary first line. The cross-coupled latch circuit is configured to receive write data via the first line, and to latch the write data during a data write operation. The write latch circuit is coupled to the cross-coupled latch circuit, and configured to store the write data in the resistive memory cell via a second line during the data write operation.

4. 发明申请

US20080252386A1 Quadrature-phase voltage controlled oscillator 失效
标题翻译：正交相控压振荡器
公开(公告)号：US20080252386A1
公开(公告)日：2008-10-16
申请号：US12078851
申请日：2008-04-07
申请人： Chan Kyung Kim
发明人： Chan Kyung Kim
IPC分类号： H03B27/00
CPC分类号： H03K3/0322 , H03K5/133 , H03K2005/00208 , H03K2005/00234 , H03K2005/00286 , H03L7/0995
摘要： A voltage controlled oscillator (VCO) is provided. The VCO may include a first ring oscillation circuit that may have a plurality of delay cells and may output first differential oscillation signals, and a second ring oscillation circuit that may have a plurality of delay cells and may output second differential oscillation signals. The delay cells of the first ring oscillation circuit may be respectively cross-coupled to the corresponding delay cells of the second ring oscillation circuit. Each of the delay cells may include a differential amplification circuit that may output a first differential signal based on a first control signal, and a negative resistance circuit that may be connected in parallel to a pair of output terminals of the differential amplification circuit, may receive a second differential signal, may adjust the phase of the first differential signal based on a second control signal, and may then output the first differential signal.
摘要翻译：提供压控振荡器（VCO）。 VCO可以包括可以具有多个延迟单元并且可以输出第一差分振荡信号的第一环形振荡电路，以及可以具有多个延迟单元并且可以输出第二差分振荡信号的第二环形振荡电路。第一环形振荡电路的延迟单元可以分别交叉耦合到第二环形振荡电路的对应的延迟单元。每个延迟单元可以包括差分放大电路，其可以基于第一控制信号输出第一差分信号，并且可以并联连接到差分放大电路的一对输出端子的负电阻电路可以接收第二差分信号可以基于第二控制信号调整第一差分信号的相位，然后可以输出第一差分信号。

5. 发明申请

US20080024182A1 Duty cycle correction circuit and duty cycle correction method 有权
标题翻译：占空比校正电路和占空比校正方法
公开(公告)号：US20080024182A1
公开(公告)日：2008-01-31
申请号：US11819414
申请日：2007-06-27
申请人： Hyun Su Choi , Chan Kyung Kim
发明人： Hyun Su Choi , Chan Kyung Kim
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K5/133
摘要： A duty cycle correction circuit may include an error corrector adapted to correct duty cycles of first differential analog clock signals input to a pair of input terminals based on duty cycle correction signals input to a pair of control terminals and to output second differential analog clock signals having corrected duty cycles through a pair of output terminals, an analog to digital buffer adapted to convert the second differential analog clock signals to differential digital clock signals, a duty error detector adapted to detect duty cycles of the differential digital clock signals and to output a N bit digital signal, and a duty error correction signal generator adapted to output differential control current signals having current gains controlled based on the second differential analog clock signals and the N bit digital signal to the pair of control terminals as the duty cycle correction signals.
摘要翻译：占空比校正电路可以包括误差校正器，其适于基于输入到一对控制端子的占空比校正信号来校正输入到一对输入端子的第一差分模拟时钟信号的占空比，并输出具有通过一对输出端子，适于将第二差分模拟时钟信号转换为差分数字时钟信号的模数转换器的校正占空比;适用于检测差分数字时钟信号的占空比并输出N 以及负载误差校正信号发生器，其适于将具有基于第二差分模拟时钟信号和N位数字信号控制的电流增益的差分控制电流信号输出到该对控制端子，作为占空比校正信号。

6. 发明授权

US07683726B2 Quadrature-phase voltage controlled oscillator 失效
标题翻译：正交相控压振荡器
公开(公告)号：US07683726B2
公开(公告)日：2010-03-23
申请号：US12078851
申请日：2008-04-07
申请人： Chan Kyung Kim
发明人： Chan Kyung Kim
IPC分类号： H03B27/00
CPC分类号： H03K3/0322 , H03K5/133 , H03K2005/00208 , H03K2005/00234 , H03K2005/00286 , H03L7/0995
摘要： A voltage controlled oscillator (VCO) is provided. The VCO may include a first ring oscillation circuit that may have a plurality of delay cells and may output first differential oscillation signals, and a second ring oscillation circuit that may have a plurality of delay cells and may output second differential oscillation signals. The delay cells of the first ring oscillation circuit may be respectively cross-coupled to the corresponding delay cells of the second ring oscillation circuit. Each of the delay cells may include a differential amplification circuit that may output a first differential signal based on a first control signal, and a negative resistance circuit that may be connected in parallel to a pair of output terminals of the differential amplification circuit, may receive a second differential signal, may adjust the phase of the first differential signal based on a second control signal, and may then output the first differential signal.
摘要翻译：提供压控振荡器（VCO）。 VCO可以包括可以具有多个延迟单元并且可以输出第一差分振荡信号的第一环形振荡电路，以及可以具有多个延迟单元并且可以输出第二差分振荡信号的第二环形振荡电路。第一环形振荡电路的延迟单元可以分别交叉耦合到第二环形振荡电路的对应的延迟单元。每个延迟单元可以包括差分放大电路，其可以基于第一控制信号输出第一差分信号，并且可以并联连接到差分放大电路的一对输出端子的负电阻电路可以接收第二差分信号可以基于第二控制信号调整第一差分信号的相位，然后可以输出第一差分信号。

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