专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07415031B2 Data link/physical layer packet diversion and insertion 失效
标题翻译：数据链路/物理层分组转发和插入
公开(公告)号：US07415031B2
公开(公告)日：2008-08-19
申请号：US09918691
申请日：2001-07-30
申请人： Donald R. Primrose , I. Claude Denton
发明人： Donald R. Primrose , I. Claude Denton
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/9047 , H04L49/90 , H04L49/9094
摘要： A buffering structure including a number of storage structures and associated diversion and/or insertion logic, is provided to facilitate one or more selected ones of post-switching, pre-medium placement, diversion and/or insertion of egress packets, and post-medium extraction, pre-switching, diversion and/or insertion of ingress packets, during data link/physical layer processing of networking traffic. In selected applications, the buffering structure is provided as an integral part of a single ASIC multi-protocol networking processor having data link/physical layer processing components for a number of datacom and telecom protocols. In one of the selected applications, the single ASIC multi-protocol networking processor is employed in conjunction with other optical and electro components to form an integral optical networking module in support of optical-electro networking for the datacom/telecom protocols.
摘要翻译：提供了包括多个存储结构和相关联的转移和/或插入逻辑的缓冲结构，以便于一个或多个选择的后切换，预介质放置，出口和/或插入出口分组以及后介质在网络流量的数据链路/物理层处理期间，提取，预切换，引入和/或插入入口数据包。在所选择的应用中，缓冲结构被提供为具有用于多个数据通信和电信协议的数据链路/物理层处理组件的单个ASIC多协议网络处理器的组成部分。在所选择的应用之一中，单个ASIC多协议网络处理器与其他光学和电子部件结合使用，以形成一个整体光网络模块，以支持数据通信/电信协议的光电组网。

2. 发明授权

US07688839B2 Data link/physical layer packet buffering and flushing 有权
公开(公告)号：US07688839B2
公开(公告)日：2010-03-30
申请号：US11511944
申请日：2006-08-28
申请人： Donald R. Primrose , I. Claude Denton
发明人： Donald R. Primrose , I. Claude Denton
IPC分类号： H04L12/28
CPC分类号： H04L49/9078 , H04L49/30 , H04L49/90 , H04L49/9047
摘要： A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

3. 发明授权

US07646782B1 Data link/physical layer packet buffering and flushing 有权
标题翻译：数据链路/物理层数据包缓冲和冲洗
公开(公告)号：US07646782B1
公开(公告)日：2010-01-12
申请号：US09918931
申请日：2001-07-30
申请人： Donald R. Primrose , I. Claude Denton
发明人： Donald R. Primrose , I. Claude Denton
IPC分类号： H04L12/28
CPC分类号： H04L49/9078 , H04L49/30 , H04L49/90 , H04L49/9047
摘要： A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.
摘要翻译：提供了包括至少第一FIFO存储结构的缓冲结构，用于对未被引导的出口分组和未发送的入口分组中的至少一个进行分级。缓冲结构还包括至少第一相关联的分组丢弃逻辑以选择性地实现第一FIFO存储结构的头部或尾部刷新。在各种实施例中，还提供一个或多个附加FIFO存储结构以对一个或多个转发和/或插入出口/入口分组进行分级。用于分级转移出口/入口分组的那些同样具有相关联的分组丢弃逻辑以执行这些附加FIFO结构的尾部刷新。在一个应用中，缓冲结构由多协议网络处理器采用，这又由光网络模块采用。

4. 发明授权

US08194691B2 Data link/physical layer packet buffering and flushing 有权
标题翻译：数据链路/物理层数据包缓冲和冲洗
公开(公告)号：US08194691B2
公开(公告)日：2012-06-05
申请号：US11512028
申请日：2006-08-28
申请人： Donald R. Primrose , I. Claude Denton
发明人： Donald R. Primrose , I. Claude Denton
IPC分类号： H04L12/56
CPC分类号： H04L49/9078 , H04L49/30 , H04L49/90 , H04L49/9047
摘要： A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.
摘要翻译：提供了包括至少第一FIFO存储结构的缓冲结构，用于对未被引导的出口分组和未发送的入口分组中的至少一个进行分级。缓冲结构还包括至少第一相关联的分组丢弃逻辑以选择性地实现第一FIFO存储结构的头部或尾部刷新。在各种实施例中，还提供一个或多个附加FIFO存储结构以对一个或多个转发和/或插入出口/入口分组进行分级。用于分级转移出口/入口分组的那些同样具有相关联的分组丢弃逻辑以执行这些附加FIFO结构的尾部刷新。在一个应用中，缓冲结构由多协议网络处理器采用，这又由光网络模块采用。

5. 再颁专利

USRE40660E1 Configurable glueless microprocessor interface 有权
标题翻译：可配置的无缝微处理器接口
公开(公告)号：USRE40660E1
公开(公告)日：2009-03-10
申请号：US11652469
申请日：2007-01-10
申请人： Donald R. Primrose
发明人： Donald R. Primrose
IPC分类号： G06F13/00
CPC分类号： G06F13/4068
摘要： A host control interface for use in interfacing an external host processor with internal control/status registers of an integrated circuit is provided. In accordance with the teachings of the present invention, the control interface selectively couples the integrated circuit with an interchangeable one of a variety of host processor types. In one embodiment, the control interface supports processors having a multiplexed address/data port as well as processors having separate address and data ports. Similarly, in one embodiment, the control interface supports processors utilizing a transfer start indication signal in cooperation with a read/write signal, as well as processors utilizing separate read/write strobes.
摘要翻译：提供了用于将外部主机处理器与集成电路的内部控制/状态寄存器连接的主机控制接口。根据本发明的教导，控制接口选择性地将集成电路与多种主机处理器类型中的可互换的一种耦合。在一个实施例中，控制接口支持具有复用的地址/数据端口的处理器以及具有单独的地址和数据端口的处理器。类似地，在一个实施例中，控制接口支持利用与读/写信号协同的传送开始指示信号的处理器，以及利用分开的读/写选通的处理器。

6. 发明授权

US06842816B1 Configurable glueless microprocessor interface 有权
标题翻译：可配置的无缝微处理器接口
公开(公告)号：US06842816B1
公开(公告)日：2005-01-11
申请号：US09920246
申请日：2001-07-31
申请人： Donald R. Primrose
发明人： Donald R. Primrose
IPC分类号： G06F13/00 , G06F13/14 , G06F13/40
CPC分类号： G06F13/4068
摘要： A host control interface for use in interfacing an external host processor with internal control/status registers of an integrated circuit is provided. In accordance with the teachings of the present invention, the control interface selectively couples the integrated circuit with an interchangeable one of a variety of host processor types. In one embodiment, the control interface supports processors having a multiplexed address/data port as well as processors having separate address and data ports. Similarly, in one embodiment, the control interface supports processors utilizing a transfer start indication signal in cooperation with a read/write signal, as well as processors utilizing separate read/write strobes.
摘要翻译：提供了用于将外部主机处理器与集成电路的内部控制/状态寄存器连接的主机控制接口。根据本发明的教导，控制接口选择性地将集成电路与多种主机处理器类型中的可互换的一种耦合。在一个实施例中，控制接口支持具有复用的地址/数据端口的处理器以及具有单独的地址和数据端口的处理器。类似地，在一个实施例中，控制接口支持利用与读/写信号协同的传送开始指示信号的处理器，以及利用分开的读/写选通的处理器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式