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1. 发明申请

US20130043534A1 HIGH DENSITY LATERAL DMOS AND ASSOCIATED METHOD FOR MAKING 有权
标题翻译：高密度横向DMOS及相关方法制作
公开(公告)号：US20130043534A1
公开(公告)日：2013-02-21
申请号：US13213011
申请日：2011-08-18
申请人： Donald R. Disney , Lei Zhang , Tiesheng Li
发明人： Donald R. Disney , Lei Zhang , Tiesheng Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66689 , H01L29/66696
摘要： The present disclosure discloses a lateral DMOS with recessed source contact and method for making the same. The lateral DMOS comprises a recessed source contact which has a portion recessed into a source region to reach a body region of the lateral DMOS. The lateral DMOS according to various embodiments of the present invention may have greatly reduced size and may be cost saving for fabrication.
摘要翻译：本公开公开了一种具有凹陷源触点的横向DMOS及其制造方法。横向DMOS包括凹入的源极接触件，其具有凹入到源区域中的部分以到达侧向DMOS的主体区域。根据本发明的各种实施例的横向DMOS可以具有大大减小的尺寸，并且可以节省制造成本。

2. 发明授权

US07977193B1 Trench-gate MOSFET with capacitively depleted drift region 有权
标题翻译：具有电容耗尽漂移区的沟槽栅极MOSFET
公开(公告)号：US07977193B1
公开(公告)日：2011-07-12
申请号：US12908774
申请日：2010-10-20
申请人： Donald R. Disney , Tiesheng Li , Lei Zhang
发明人： Donald R. Disney , Tiesheng Li , Lei Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42376 , H01L29/66734
摘要： A trench-gate metal oxide semiconductor field-effect transistor includes a field plate that extends into a drift region of the transistor. The field plate is configured to deplete the drift region when the transistor is in the OFF-state. The field plate is formed in a field plate trench. The field plate trench may be formed using a self-aligned etch process. The conductive material of the field plate and gate of the transistor may be deposited in the same deposition process step. The conductive material may be etched thereafter to form the field plate and the gate in the same etch process step.
摘要翻译：沟槽栅极金属氧化物半导体场效应晶体管包括延伸到晶体管的漂移区域的场板。场板配置为在晶体管处于截止状态时耗尽漂移区域。场板形成在场板沟槽中。场板沟槽可以使用自对准蚀刻工艺形成。晶体管的场板和栅极的导电材料可以在相同的沉积工艺步骤中沉积。之后可以蚀刻导电材料，以在相同的蚀刻工艺步骤中形成场板和栅极。

3. 发明授权

US08546879B2 High density lateral DMOS with recessed source contact 有权
标题翻译：高密度横向DMOS具有凹陷源接触
公开(公告)号：US08546879B2
公开(公告)日：2013-10-01
申请号：US13213011
申请日：2011-08-18
申请人： Donald R. Disney , Lei Zhang , Tiesheng Li
发明人： Donald R. Disney , Lei Zhang , Tiesheng Li
IPC分类号： H01L29/66
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66689 , H01L29/66696
摘要： The present disclosure discloses a lateral DMOS with recessed source contact and method for making the same. The lateral DMOS comprises a recessed source contact which has a portion recessed into a source region to reach a body region of the lateral DMOS. The lateral DMOS according to various embodiments of the present invention may have greatly reduced size and may be cost saving for fabrication.
摘要翻译：本公开公开了一种具有凹陷源触点的横向DMOS及其制造方法。横向DMOS包括凹入的源极接触件，其具有凹入到源区域中的部分以到达侧向DMOS的主体区域。根据本发明的各种实施例的横向DMOS可以具有大大减小的尺寸，并且可以节省制造成本。

4. 发明申请

US20120280311A1 TRENCH-GATE MOSFET DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译： TRENCH-GATE MOSFET器件及其制造方法
公开(公告)号：US20120280311A1
公开(公告)日：2012-11-08
申请号：US13462397
申请日：2012-05-02
申请人： Lei Zhang , Donald R. Disney , Tiesheng Li , Rongyao Ma
发明人： Lei Zhang , Donald R. Disney , Tiesheng Li , Rongyao Ma
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/2652 , H01L21/266 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7805
摘要： The embodiments of the present disclosure disclose a trench-gate MOSFET device and the method for making the trench-gate MOSFET device. The trench-gate MOSFET device comprises a curving dopant profile formed between the body region and the epitaxial layer so that the portion of the body region under the source metal contact has a smaller vertical thickness than the other portion of the body region. The trench-gate MOSFET device in accordance with the embodiments of the present disclosure has improved UIS capability compared with the traditional trench-gate MOSFET device.
摘要翻译：本公开的实施例公开了沟槽栅极MOSFET器件和制造沟槽栅极MOSFET器件的方法。沟槽栅极MOSFET器件包括在体区和外延层之间形成的弯曲掺杂剂分布，使得源极金属接触下方的主体区域的部分的垂直厚度小于身体区域的另一部分。根据本公开实施例的沟槽栅MOSFET MOSFET器件与传统沟槽栅极MOSFET器件相比具有改进的UIS能力。

5. 发明授权

US08841708B2 Method and system for a GAN vertical JFET with self-aligned source metallization 有权
标题翻译：具有自对准源金属化的GAN垂直JFET的方法和系统
公开(公告)号：US08841708B2
公开(公告)日：2014-09-23
申请号：US13468332
申请日：2012-05-10
申请人： Donald R. Disney , Richard J. Brown , Hui Nie
发明人： Donald R. Disney , Richard J. Brown , Hui Nie
IPC分类号： H01L29/808
CPC分类号： H01L29/41741 , H01L29/2003 , H01L29/42316 , H01L29/66446 , H01L29/8083
摘要： A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.
摘要翻译：半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底的沟道结构。沟道结构包括第一III族氮化物外延材料，其特征在于一个或多个沟道侧壁。半导体器件还包括耦合到沟道结构的源极区域。源区包括第二III族氮化物外延材料。所述半导体器件还包括耦合到所述一个或多个沟道侧壁的III族氮化物栅极结构，与所述III族氮化物栅极结构电接触的栅极金属结构以及覆盖所述栅极金属结构的至少一部分的介电层。电介质层的顶表面与源区的顶表面基本上共面。

6. 发明授权

US08698164B2 Vertical GaN JFET with gate source electrodes on regrown gate 有权
标题翻译：在再生栅上具有栅极源电极的垂直GaN JFET
公开(公告)号：US08698164B2
公开(公告)日：2014-04-15
申请号：US13315720
申请日：2011-12-09
申请人： Donald R. Disney , Hui Nie , Isik C. Kizilyalli , Richard J. Brown
发明人： Donald R. Disney , Hui Nie , Isik C. Kizilyalli , Richard J. Brown
IPC分类号： H01L29/808 , H01L21/335
CPC分类号： H01L29/8083 , H01L29/0623 , H01L29/2003 , H01L29/402 , H01L29/66446 , H01L29/66462 , H01L29/66909 , H01L29/66924
摘要： A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.
摘要翻译：半导体结构包括具有第一表面和第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。第一电极电耦合到GaN衬底的第二表面。半导体结构还包括耦合到GaN衬底的第一表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN层。第一GaN外延层包括沟道区。第二GaN外延层包括栅极区域和边缘端接结构。耦合到栅极区域的第二电极和耦合到沟道区域的第三电极都设置在边缘端接结构内。

7. 发明授权

US08513087B2 Processes for forming isolation structures for integrated circuit devices 有权
标题翻译：用于形成用于集成电路器件的隔离结构的工艺
公开(公告)号：US08513087B2
公开(公告)日：2013-08-20
申请号：US13095019
申请日：2011-04-27
申请人： Donald R. Disney , Richard K. Williams
发明人： Donald R. Disney , Richard K. Williams
IPC分类号： H01L21/76
CPC分类号： H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823878 , H01L21/823892 , H01L29/1004 , H01L29/41708 , H01L29/732
摘要： Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.
摘要翻译：用于形成用于半导体器件的隔离结构的工艺包括形成浸没的底部隔离区域和一起封装衬底的隔离袋状物的沟槽。一个过程将沟槽对准地板隔离区域。在另一种方法中，在隔离的袋中形成第二较窄的沟槽，并且填充介电材料，同时沉积电介质材料以便使第一沟槽的壁和底板成线。衬底不含有外延层，从而克服了与其制造相关的许多问题。

8. 发明申请

US20130032895A1 HIGH-VOLTAGE TRANSISTOR DEVICE AND ASSOCIATED METHOD FOR MANUFACTURING 有权
标题翻译：高压晶体管器件及相关制造方法
公开(公告)号：US20130032895A1
公开(公告)日：2013-02-07
申请号：US13195199
申请日：2011-08-01
申请人： Donald R. Disney , Ognjen Milic , Kun Yi
发明人： Donald R. Disney , Ognjen Milic , Kun Yi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/1083 , H01L29/404 , H01L29/405 , H01L29/66659
摘要： A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.
摘要翻译：高压晶体管器件包括在高压晶体管器件的漏极区域和源极区域之间的第一阱区域上的螺旋电阻场板，其中螺旋电阻场板通过第一隔离与第一阱区域分离并且耦合在漏极区域和源极区域之间。高压晶体管器件还包括在螺旋电阻场板上的多个第一场板，每个第一场板覆盖螺旋电阻场板的一个或多个段，其中多个第一场板与螺旋电阻隔离并且其中所述多个第一场板彼此隔离，并且起始第一场板连接到所述源极区域。

9. 发明申请

US20120314453A1 ELECTRONIC CIRCUIT CONTROL ELEMENT WITH TAP ELEMENT 失效
标题翻译：带有元件的电子电路控制元件
公开(公告)号：US20120314453A1
公开(公告)日：2012-12-13
申请号：US13571209
申请日：2012-08-09
申请人： Donald R. Disney
发明人： Donald R. Disney
IPC分类号： H01L27/088 , H02M3/335
CPC分类号： H01L29/7803 , G05F1/14 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/407 , H01L29/42368 , H01L29/7802 , H01L29/7813 , H02M1/36 , H02M3/335 , H02M3/33507 , H02M3/33553 , H02M3/33561 , H02M2001/0009
摘要： An example control element for use in a power supply includes a high-voltage transistor and a control circuit to control switching of the high-voltage transistor. The high-voltage transistor includes a drain region, source region, tap region, drift region, and tap drift region, all of a first conductivity type. The transistor also includes a body region of a second conductivity type. An insulated gate is included in the transistor such that when the insulated gate is biased a channel is formed across the body region to form a conduction path between the source region and the drift region. A voltage at the tap region with respect to the source region is substantially constant and less than a voltage at the drain region with respect to the source region in response to the voltage at the drain region exceeding a pinch off voltage.
摘要翻译：用于电源的示例性控制元件包括高压晶体管和用于控制高压晶体管的开关的控制电路。高压晶体管包括漏区，源区，抽头区，漂移区和抽头漂移区，全部为第一导电类型。晶体管还包括第二导电类型的体区。绝缘栅极包括在晶体管中，使得当绝缘栅极被偏置时，跨越体区域形成沟道以在源极区域和漂移区域之间形成传导路径。相对于源极区域的抽头区域处的电压基本上是恒定的，并且响应于漏极区域处的电压超过夹断电压而小于相对于源极区域的漏极区域处的电压。

10. 发明申请

US20110084333A1 POWER DEVICES WITH SUPER JUNCTIONS AND ASSOCIATED METHODS MANUFACTURING 有权
标题翻译：具有超级连接的功率器件和相关方法制造
公开(公告)号：US20110084333A1
公开(公告)日：2011-04-14
申请号：US12576150
申请日：2009-10-08
申请人： Donald R. Disney , Michael R. Hsing
发明人： Donald R. Disney , Michael R. Hsing
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7802 , H01L21/2254 , H01L21/2256 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0878 , H01L29/66712
摘要： Power devices with super junctions and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a power device includes forming an epitaxial layer on a substrate material and forming a trench in the epitaxial layer. The trench has a first sidewall, a second sidewall, and a bottom between the first and second sidewalls. The method also includes forming an insulation material on at least one of the first and second sidewalls of the trench and diffusing a dopant into the epitaxial layer via at least one of the first and second sidewalls of the trench via the insulation material.
摘要翻译：本文公开了具有超连接和相关制造方法的功率器件。在一个实施例中，形成功率器件的方法包括在衬底材料上形成外延层并在外延层中形成沟槽。沟槽具有第一侧壁，第二侧壁和位于第一和第二侧壁之间的底部。该方法还包括在沟槽的第一和第二侧壁中的至少一个上形成绝缘材料，并且经由绝缘材料经由沟槽的第一和第二侧壁中的至少一个将掺杂剂扩散到外延层中。

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