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1. 发明申请

US20130032895A1 HIGH-VOLTAGE TRANSISTOR DEVICE AND ASSOCIATED METHOD FOR MANUFACTURING 有权
标题翻译：高压晶体管器件及相关制造方法
公开(公告)号：US20130032895A1
公开(公告)日：2013-02-07
申请号：US13195199
申请日：2011-08-01
申请人： Donald R. Disney , Ognjen Milic , Kun Yi
发明人： Donald R. Disney , Ognjen Milic , Kun Yi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/1083 , H01L29/404 , H01L29/405 , H01L29/66659
摘要： A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.
摘要翻译：高压晶体管器件包括在高压晶体管器件的漏极区域和源极区域之间的第一阱区域上的螺旋电阻场板，其中螺旋电阻场板通过第一隔离与第一阱区域分离并且耦合在漏极区域和源极区域之间。高压晶体管器件还包括在螺旋电阻场板上的多个第一场板，每个第一场板覆盖螺旋电阻场板的一个或多个段，其中多个第一场板与螺旋电阻隔离并且其中所述多个第一场板彼此隔离，并且起始第一场板连接到所述源极区域。

2. 发明授权

US08759912B2 High-voltage transistor device 有权
标题翻译：高压晶体管器件
公开(公告)号：US08759912B2
公开(公告)日：2014-06-24
申请号：US13195199
申请日：2011-08-01
申请人： Donald R. Disney , Ognjen Milic , Kun Yi
发明人： Donald R. Disney , Ognjen Milic , Kun Yi
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/1083 , H01L29/404 , H01L29/405 , H01L29/66659
摘要： A high-voltage transistor device comprises a spiral resistive field plate over a first well region between a drain region and a source region of the high-voltage transistor device, wherein the spiral resistive field plate is separated from the first well region by a first isolation layer, and is coupled between the drain region and the source region. The high-voltage transistor device further comprises a plurality of first field plates over the spiral resistive field plate with each first field plate covering one or more segments of the spiral resistive field plate, wherein the plurality of first field plates are isolated from the spiral resistive field plate by a first dielectric layer, and wherein the plurality of first field plates are isolated from each other, and a starting first field plate is connected to the source region.
摘要翻译：高压晶体管器件包括在高压晶体管器件的漏极区域和源极区域之间的第一阱区域上的螺旋电阻场板，其中螺旋形电阻场板通过第一隔离与第一阱区域分离并且耦合在漏极区域和源极区域之间。高压晶体管器件还包括在螺旋电阻场板上的多个第一场板，每个第一场板覆盖螺旋电阻场板的一个或多个段，其中多个第一场板与螺旋电阻隔离并且其中所述多个第一场板彼此隔离，并且起始第一场板连接到所述源极区域。

3. 发明申请

US20110062489A1 POWER DEVICE WITH SELF-ALIGNED SILICIDE CONTACT 审中-公开
标题翻译：具有自对准硅胶触点的电源装置
公开(公告)号：US20110062489A1
公开(公告)日：2011-03-17
申请号：US12557841
申请日：2009-09-11
申请人： Donald R. Disney , Ognjen Milic
发明人： Donald R. Disney , Ognjen Milic
IPC分类号： H01L29/739 , H01L29/78 , H01L21/82
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/66333 , H01L29/665 , H01L29/66719 , H01L29/66727 , H01L29/7395
摘要： An improved power device with a self-aligned suicide and a method for fabricating the device are disclosed. An example power device is a vertical power device that includes contacts formed on gate and body contact regions by an at least substantially self-aligned silicidation (e.g., salicide) process. The example device may also include one or more sidewall spacers that are each at least substantially aligned between edges of the gate region and the body contact region. The body contact region may also be implanted into the device in at least substantial self-alignment to the sidewall spacer. The method may also include an at least substantially self-aligned silicon etch.
摘要翻译：公开了一种具有自对准硅化物的改进的功率器件及其制造方法。示例性功率器件是垂直功率器件，其包括通过至少基本上自对准的硅化（例如自对准硅）工艺在栅极和体接触区域上形成的触点。示例性装置还可以包括一个或多个侧壁间隔件，每个侧壁间隔件至少基本上对准在栅极区域和主体接触区域的边缘之间。身体接触区域也可以以至少基本上与对侧隔离物自对准的方式植入到装置中。该方法还可以包括至少基本上自对准的硅蚀刻。

4. 发明申请

US20130043532A1 LATERAL HIGH-VOLTAGE TRANSISTOR AND ASSOCIATED METHOD FOR MANUFACTURING 有权
标题翻译：横向高压晶体管及相关制造方法
公开(公告)号：US20130043532A1
公开(公告)日：2013-02-21
申请号：US13212097
申请日：2011-08-17
申请人： Donald R. Disney , Ognjen Milic
发明人： Donald R. Disney , Ognjen Milic
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/063 , H01L29/0623 , H01L29/0847 , H01L29/1083 , H01L29/405 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： The present disclosure discloses a lateral high-voltage transistor and associated method for making the same. The lateral high-voltage transistor comprises a semiconductor layer of a first conductivity type; a source region of a second conductivity type opposite to the first conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer separated from the source region; a first isolation layer atop the semiconductor layer between the source region and the drain region; a first well region of the second conductivity type surrounding the drain region, extending towards the source region and separated from the source region; a second well region of the first conductivity type surrounding the source region; a gate positioned atop the first isolation layer above the second well region and an adjacent portion of the first well region; and a first buried layer of the first conductivity type under the first well region adjacent to the source region side of the lateral high-voltage transistor. A JFET is formed using the gate as a JFET top gate and the first buried layer as a JFET bottom gate.
摘要翻译：本公开公开了一种横向高压晶体管及其制造方法。横向高压晶体管包括第一导电类型的半导体层; 在半导体层中与第一导电类型相反的第二导电类型的源极区; 所述半导体层中的所述第二导电类型的漏极区域与所述源极区域分离; 在源极区域和漏极区域之间的半导体层顶部的第一隔离层; 围绕所述漏极区的所述第二导电类型的第一阱区，朝向所述源极区延伸并与所述源极区分离; 围绕源区的第一导电类型的第二阱区; 位于所述第二阱区域上方的所述第一隔离层顶部的栅极和所述第一阱区域的相邻部分; 以及与所述横向高压晶体管的源极侧相邻的所述第一阱区域之下的所述第一导电类型的第一掩埋层。使用栅极作为JFET顶栅形成JFET，并且将第一掩埋层形成为JFET底栅。

5. 发明授权

US08686503B2 Lateral high-voltage transistor and associated method for manufacturing 有权
标题翻译：横向高压晶体管及其制造方法
公开(公告)号：US08686503B2
公开(公告)日：2014-04-01
申请号：US13212097
申请日：2011-08-17
申请人： Donald R. Disney , Ognjen Milic
发明人： Donald R. Disney , Ognjen Milic
IPC分类号： H01L29/66
CPC分类号： H01L29/063 , H01L29/0623 , H01L29/0847 , H01L29/1083 , H01L29/405 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： The present disclosure discloses a lateral high-voltage transistor and associated method for making the same. The lateral high-voltage transistor comprises a semiconductor layer of a first conductivity type; a source region of a second conductivity type opposite to the first conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer separated from the source region; a first isolation layer atop the semiconductor layer between the source region and the drain region; a first well region of the second conductivity type surrounding the drain region, extending towards the source region and separated from the source region; a second well region of the first conductivity type surrounding the source region; a gate positioned atop the first isolation layer above the second well region and an adjacent portion of the first well region; and a first buried layer of the first conductivity type under the first well region adjacent to the source region side of the lateral high-voltage transistor. A JFET is formed using the gate as a JFET top gate and the first buried layer as a JFET bottom gate.
摘要翻译：本公开公开了一种横向高压晶体管及其制造方法。横向高压晶体管包括第一导电类型的半导体层; 在半导体层中与第一导电类型相反的第二导电类型的源极区; 所述半导体层中的所述第二导电类型的漏极区域与所述源极区域分离; 在源极区域和漏极区域之间的半导体层顶部的第一隔离层; 围绕所述漏极区的所述第二导电类型的第一阱区，朝向所述源极区延伸并与所述源极区分离; 围绕源区的第一导电类型的第二阱区; 位于所述第二阱区域上方的所述第一隔离层顶部的栅极和所述第一阱区域的相邻部分; 以及与所述横向高压晶体管的源极侧相邻的所述第一阱区域之下的所述第一导电类型的第一掩埋层。使用栅极作为JFET顶栅形成JFET，并且将第一掩埋层形成为JFET底栅。

6. 发明申请

US20130161740A1 Lateral High-Voltage Transistor with Buried Resurf Layer and Associated Method for Manufacturing the Same 审中-公开
标题翻译：具有掩埋层的横向高压晶体管及其制造方法
公开(公告)号：US20130161740A1
公开(公告)日：2013-06-27
申请号：US13332862
申请日：2011-12-21
申请人： Donald R. Disney , Ognjen Milic
发明人： Donald R. Disney , Ognjen Milic
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0634 , H01L29/405 , H01L29/66659 , H01L29/7835
摘要： A lateral high-voltage transistor comprising a semiconductor layer of a first conductivity type; a source region of a second conductivity type in the semiconductor layer; a drain region of the second conductivity type in the semiconductor layer; a first isolation layer atop the semiconductor layer between the source and the drain regions; a first well region of the second conductivity type surrounding the drain region; a gate positioned atop the first isolation layer adjacent to the source region; a spiral resistive field plate atop the first isolation layer spiraling between the drain region and the gate, wherein the spiral resistive field plate is coupled in series to the source and drain regions; and a buried layer of the first conductivity type in the first well region, wherein the buried layer is buried beneath a top surface of the first well region below the spiral resistive field plate.
摘要翻译：一种横向高压晶体管，包括第一导电类型的半导体层; 半导体层中的第二导电类型的源极区; 半导体层中的第二导电类型的漏极区; 源极和漏极区域之间的半导体层顶部的第一隔离层; 围绕所述漏极区的所述第二导电类型的第一阱区; 位于与源区相邻的第一隔离层顶上的栅极; 在所述漏极区和所述栅极之间螺旋化的所述第一隔离层顶部的螺旋电阻场板，其中所述螺旋电阻场板串联耦合到所述源极和漏极区; 以及第一阱区域中的第一导电类型的掩埋层，其中所述掩埋层埋在所述螺旋电阻场板下方的所述第一阱区域的顶表面之下。

7. 发明授权

US08841708B2 Method and system for a GAN vertical JFET with self-aligned source metallization 有权
标题翻译：具有自对准源金属化的GAN垂直JFET的方法和系统
公开(公告)号：US08841708B2
公开(公告)日：2014-09-23
申请号：US13468332
申请日：2012-05-10
申请人： Donald R. Disney , Richard J. Brown , Hui Nie
发明人： Donald R. Disney , Richard J. Brown , Hui Nie
IPC分类号： H01L29/808
CPC分类号： H01L29/41741 , H01L29/2003 , H01L29/42316 , H01L29/66446 , H01L29/8083
摘要： A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.
摘要翻译：半导体器件包括III族氮化物衬底和耦合到III族氮化物衬底的沟道结构。沟道结构包括第一III族氮化物外延材料，其特征在于一个或多个沟道侧壁。半导体器件还包括耦合到沟道结构的源极区域。源区包括第二III族氮化物外延材料。所述半导体器件还包括耦合到所述一个或多个沟道侧壁的III族氮化物栅极结构，与所述III族氮化物栅极结构电接触的栅极金属结构以及覆盖所述栅极金属结构的至少一部分的介电层。电介质层的顶表面与源区的顶表面基本上共面。

8. 发明授权

US08698164B2 Vertical GaN JFET with gate source electrodes on regrown gate 有权
标题翻译：在再生栅上具有栅极源电极的垂直GaN JFET
公开(公告)号：US08698164B2
公开(公告)日：2014-04-15
申请号：US13315720
申请日：2011-12-09
申请人： Donald R. Disney , Hui Nie , Isik C. Kizilyalli , Richard J. Brown
发明人： Donald R. Disney , Hui Nie , Isik C. Kizilyalli , Richard J. Brown
IPC分类号： H01L29/808 , H01L21/335
CPC分类号： H01L29/8083 , H01L29/0623 , H01L29/2003 , H01L29/402 , H01L29/66446 , H01L29/66462 , H01L29/66909 , H01L29/66924
摘要： A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.
摘要翻译：半导体结构包括具有第一表面和第二表面的GaN衬底。 GaN衬底的特征在于第一导电类型和第一掺杂剂浓度。第一电极电耦合到GaN衬底的第二表面。半导体结构还包括耦合到GaN衬底的第一表面的第一导电类型的第一GaN外延层和耦合到第一GaN外延层的第二导电类型的第二GaN层。第一GaN外延层包括沟道区。第二GaN外延层包括栅极区域和边缘端接结构。耦合到栅极区域的第二电极和耦合到沟道区域的第三电极都设置在边缘端接结构内。

9. 发明授权

US08513087B2 Processes for forming isolation structures for integrated circuit devices 有权
标题翻译：用于形成用于集成电路器件的隔离结构的工艺
公开(公告)号：US08513087B2
公开(公告)日：2013-08-20
申请号：US13095019
申请日：2011-04-27
申请人： Donald R. Disney , Richard K. Williams
发明人： Donald R. Disney , Richard K. Williams
IPC分类号： H01L21/76
CPC分类号： H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823878 , H01L21/823892 , H01L29/1004 , H01L29/41708 , H01L29/732
摘要： Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.
摘要翻译：用于形成用于半导体器件的隔离结构的工艺包括形成浸没的底部隔离区域和一起封装衬底的隔离袋状物的沟槽。一个过程将沟槽对准地板隔离区域。在另一种方法中，在隔离的袋中形成第二较窄的沟槽，并且填充介电材料，同时沉积电介质材料以便使第一沟槽的壁和底板成线。衬底不含有外延层，从而克服了与其制造相关的许多问题。

10. 发明申请

US20120314453A1 ELECTRONIC CIRCUIT CONTROL ELEMENT WITH TAP ELEMENT 失效
标题翻译：带有元件的电子电路控制元件
公开(公告)号：US20120314453A1
公开(公告)日：2012-12-13
申请号：US13571209
申请日：2012-08-09
申请人： Donald R. Disney
发明人： Donald R. Disney
IPC分类号： H01L27/088 , H02M3/335
CPC分类号： H01L29/7803 , G05F1/14 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/407 , H01L29/42368 , H01L29/7802 , H01L29/7813 , H02M1/36 , H02M3/335 , H02M3/33507 , H02M3/33553 , H02M3/33561 , H02M2001/0009
摘要： An example control element for use in a power supply includes a high-voltage transistor and a control circuit to control switching of the high-voltage transistor. The high-voltage transistor includes a drain region, source region, tap region, drift region, and tap drift region, all of a first conductivity type. The transistor also includes a body region of a second conductivity type. An insulated gate is included in the transistor such that when the insulated gate is biased a channel is formed across the body region to form a conduction path between the source region and the drift region. A voltage at the tap region with respect to the source region is substantially constant and less than a voltage at the drain region with respect to the source region in response to the voltage at the drain region exceeding a pinch off voltage.
摘要翻译：用于电源的示例性控制元件包括高压晶体管和用于控制高压晶体管的开关的控制电路。高压晶体管包括漏区，源区，抽头区，漂移区和抽头漂移区，全部为第一导电类型。晶体管还包括第二导电类型的体区。绝缘栅极包括在晶体管中，使得当绝缘栅极被偏置时，跨越体区域形成沟道以在源极区域和漂移区域之间形成传导路径。相对于源极区域的抽头区域处的电压基本上是恒定的，并且响应于漏极区域处的电压超过夹断电压而小于相对于源极区域的漏极区域处的电压。

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