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1. 发明授权

US07045453B2 Very low effective dielectric constant interconnect structures and methods for fabricating the same 失效
标题翻译：非常低的有效介电常数互连结构及其制造方法
公开(公告)号：US07045453B2
公开(公告)日：2006-05-16
申请号：US11104764
申请日：2005-04-12
申请人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
发明人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76885 , H01L2924/0002 , H01L2924/00
摘要： A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less-robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.
摘要翻译：一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能的互连。布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中布置非常低的k和较不稳定的间隙填充电介质，使得该结构将耐用层与强度非常相似低k电介质用于互连电气性能。

2. 发明授权

US07023093B2 Very low effective dielectric constant interconnect Structures and methods for fabricating the same 有权
标题翻译：非常低的有效介电常数互连结构及其制造方法
公开(公告)号：US07023093B2
公开(公告)日：2006-04-04
申请号：US10280283
申请日：2002-10-24
申请人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
发明人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
IPC分类号： H01L23/48
CPC分类号： H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76885 , H01L2924/0002 , H01L2924/00
摘要： A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.
摘要翻译：一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能互连。布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中设置非常低的k和较不牢固的间隙填充电介质，使得该结构将耐用层与强度非常低 k电介质用于互连电性能。

3. 发明授权

US08901741B2 Interconnect structures with engineered dielectrics with nanocolumnar porosity 有权
标题翻译：互连结构与具有纳米柱孔隙度的工程电介质
公开(公告)号：US08901741B2
公开(公告)日：2014-12-02
申请号：US13531518
申请日：2012-06-23
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/522 , H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

4. 发明申请

US20090075472A1 METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS 失效
标题翻译：减轻有机电介质中等离子体损伤的方法
公开(公告)号：US20090075472A1
公开(公告)日：2009-03-19
申请号：US11857760
申请日：2007-09-19
申请人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
发明人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/02063 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02304 , H01L21/02348 , H01L21/02362 , H01L21/31138 , H01L21/31144 , H01L21/31633 , H01L21/76814 , H01L21/76826 , H01L21/76831
摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.
摘要翻译：提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽用于形成线沟槽和通孔腔的离子蚀刻。减少的线偏压对金属互连结构的电产量具有有益的影响。

5. 发明授权

US08358011B1 Interconnect structures with engineered dielectrics with nanocolumnar porosity 失效
标题翻译：互连结构与具有纳米柱孔隙度的工程电介质
公开(公告)号：US08358011B1
公开(公告)日：2013-01-22
申请号：US11899842
申请日：2007-09-07
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/48
CPC分类号： H01L23/53295 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

6. 发明申请

US20130009315A1 INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY 失效
标题翻译：具有纳米孔隙度的工程电介质的互连结构
公开(公告)号：US20130009315A1
公开(公告)日：2013-01-10
申请号：US11899842
申请日：2007-09-07
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

7. 发明申请

US20120329269A1 METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS 有权
标题翻译：减轻有机电介质中等离子体损伤的方法
公开(公告)号：US20120329269A1
公开(公告)日：2012-12-27
申请号：US13602119
申请日：2012-09-01
申请人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
发明人： John C. Arnold , Griselda Bonilla , William J. Cote , Geraud Dubois , Daniel C. Edelstein , Alfred Grill , Elbert Huang , Robert D. Miller , Satya V. Nitta , Sampath Purushothaman , E. Todd Ryan , Muthumanickam Sankarapandian , Terry A. Spooner , Willi Volksen
IPC分类号： H01L21/768
CPC分类号： H01L21/76808 , H01L21/02063 , H01L21/02126 , H01L21/02203 , H01L21/02274 , H01L21/02304 , H01L21/02348 , H01L21/02362 , H01L21/31138 , H01L21/31144 , H01L21/31633 , H01L21/76814 , H01L21/76826 , H01L21/76831
摘要： Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure.
摘要翻译：提供了最小化或消除对低k和超低k有机硅酸盐金属间电介质层的等离子体损伤的方法。等离子体损伤的降低通过在合适的点处中断蚀刻和剥离工艺流程来实现，以增加本发明的处理，其保护金属间电介质层免受等离子体条带处理期间的等离子体损伤。以这种方式减少或消除等离子体损伤区域还能够减少光致抗蚀剂中的线图案和由其形成的金属线之间的线偏压，并且由于在反应性之后的湿清洁而改变线沟槽的线宽用于形成线沟槽和通孔腔的离子蚀刻。减少的线偏压对金属互连结构的电产量具有有益的影响。

8. 发明申请

US20120261823A1 INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY 有权
标题翻译：具有纳米孔隙度的工程电介质的互连结构
公开(公告)号：US20120261823A1
公开(公告)日：2012-10-18
申请号：US13531518
申请日：2012-06-23
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

9. 发明授权

US07830010B2 Surface treatment for selective metal cap applications 有权
标题翻译：选择性金属帽应用的表面处理
公开(公告)号：US07830010B2
公开(公告)日：2010-11-09
申请号：US12062130
申请日：2008-04-03
申请人： Chih-Chao Yang , Satya V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
发明人： Chih-Chao Yang , Satya V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L21/76849 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal cap formation provides a means for controlling the selective formation of the metal cap directly on the non-recessed surface of a conductive material. That is, the selective formation of the metal cap directly on the non-recessed surface of a conductive material is enhanced since the formation rate of the metal cap on the non-recessed surface of a conductive material is greater than on the hydrophobic surface of the low k dielectric material. It is observed that the hydrophobic surface may be a result of treating a damaged surface of the dielectric material with a silylating agent prior to the selective formation of the noble metal cap or, as a result of forming a hydrophobic polymeric layer on the surface of the dielectric material prior to the selective deposition of the noble metal cap. The hydrophobic polymeric layer typically includes atoms of Si, C and O.
摘要翻译：提供了其中含有贵金属的覆盖层直接存在于嵌入低k电介质材料的导电材料的非凹陷表面上的互连结构。已经确定，在金属盖形成之前通过在低k电介质材料上形成疏水表面提供了一种用于直接控制在导电材料的非凹入表面上选择性形成金属帽的手段。也就是说，直接在导电材料的非凹入表面上选择性地形成金属帽，因为金属帽在导电材料的非凹陷表面上的形成速率大于导电材料的疏水表面上的形成速率低k电介质材料。观察到，疏水性表面可以是在选择性形成贵金属盖之前用甲硅烷基化剂处理电介质材料的损坏表面的结果，或者由于在表面上形成疏水性聚合物层在贵金属盖的选择性沉积之前的介电材料。疏水性聚合物层通常包括Si，C和O的原子。

10. 发明申请

US20090250815A1 SURFACE TREATMENT FOR SELECTIVE METAL CAP APPLICATIONS 有权
标题翻译：选择性金属盖应用的表面处理
公开(公告)号：US20090250815A1
公开(公告)日：2009-10-08
申请号：US12062130
申请日：2008-04-03
申请人： CHIH-CHAO YANG , Satya V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
发明人： CHIH-CHAO YANG , Satya V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L21/76849 , H01L21/76885 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal cap formation provides a means for controlling the selective formation of the metal cap directly on the non-recessed surface of a conductive material. That is, the selective formation of the metal cap directly on the non-recessed surface of a conductive material is enhanced since the formation rate of the metal cap on the non-recessed surface of a conductive material is greater than on the hydrophobic surface of the low k dielectric material. It is observed that the hydrophobic surface may be a result of treating a damaged surface of the dielectric material with a silylating agent prior to the selective formation of the noble metal cap or, as a result of forming a hydrophobic polymeric layer on the surface of the dielectric material prior to the selective deposition of the noble metal cap. The hydrophobic polymeric layer typically includes atoms of Si, C and O.
摘要翻译：提供了其中含有贵金属的覆盖层直接存在于嵌入低k电介质材料的导电材料的非凹陷表面上的互连结构。已经确定，在金属盖形成之前通过在低k电介质材料上形成疏水表面提供了一种用于直接控制在导电材料的非凹入表面上选择性形成金属帽的手段。也就是说，直接在导电材料的非凹入表面上选择性地形成金属帽，因为金属帽在导电材料的非凹陷表面上的形成速率大于导电材料的疏水表面上的形成速率低k电介质材料。观察到，疏水性表面可以是在选择性形成贵金属盖之前用甲硅烷基化剂处理电介质材料的损坏表面的结果，或者由于在表面上形成疏水性聚合物层在贵金属盖的选择性沉积之前的介电材料。疏水性聚合物层通常包括Si，C和O的原子。

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