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1. 发明授权

US5251321A Binary to binary coded decimal and binary coded decimal to binary conversion in a VLSI central processing unit 失效
标题翻译：在VLSI中央处理单元中二进制到二进制编码十进制和二进制编码十进制到二进制转换
公开(公告)号：US5251321A
公开(公告)日：1993-10-05
申请号：US954437
申请日：1992-09-30
申请人： Donald C. Boothroyd , Clinton B. Eckard , Ronald E. Lange , William A. Shelly , Ronald W. Yoder
发明人： Donald C. Boothroyd , Clinton B. Eckard , Ronald E. Lange , William A. Shelly , Ronald W. Yoder
IPC分类号： G06F9/30 , H03M7/12 , G06F5/06
CPC分类号： G06F9/30025 , H03M7/12
摘要： Binary-Coded-Decimal to binary (DTB) and binary to Binary Coded Decimal (BTD) instructions are executed by an address and execution (AX) chip, a decimal numeric (DN) chip, and a cache. For a DTB instruction, the DN chip receives the operand to be converted from the cache, saves the sign, and stores it in a conversion register. When a bit is converted, a Ready-to-Send signal is sent on a COMFROM bus with a Ready-to-Receive Command on a COMTO bus causes the AX chip to accept the bit and the DN chip to generate the next bit until the resultant operand is produced. If the operand to be converted is negative, the DN chip inverts each remaining bit after the first "1" to obtain a two's-complement result. The result in either case is sent to the cache. For a BTD instruction, the AX chip receives the operand to be converted from the cache, send the sign bit to the DN chip and then the bits of the operand when the Ready-to-Send and Ready to Ready-to-Receive signals are produced. The resultant operand is sent to the conversion register. If the operand is negative, all bits are inverted, and a one is added to produce the resultant in two's complement notation.
摘要翻译：二进制编码 - 十进制到二进制（DTB）和二进制到二进制编码十进制（BTD）指令由地址和执行（AX）芯片，十进制数字（DN）芯片和高速缓存执行。对于DTB指令，DN芯片接收要从缓存转换的操作数，保存该符号，并将其存储在转换寄存器中。当一个位被转换时，COMFROM总线上发送一个即时发送信号，COMTO总线上的就绪接收命令使AX芯片接受该位，并且DN芯片产生下一个位，直到产生合成操作数。如果要转换的操作数为负，则DN芯片在第一个“1”之后反转每个剩余的位，以获得二进制补码结果。任一情况下的结果都将发送到缓存。对于BTD指令，AX芯片接收要从高速缓存转换的操作数，将符号位发送到DN芯片，然后在即将发送和就绪准备就绪信号为零时，操作数的位生产。结果操作数被发送到转换寄存器。如果操作数为负，则所有位都被反转，并且添加一个位以产生以二进制补码表示的结果。

2. 发明授权

US5644761A Basic operations synchronization and local mode controller in a VLSI central processor 失效
标题翻译： VLSI中央处理器中的基本操作同步和本地模式控制器
公开(公告)号：US5644761A
公开(公告)日：1997-07-01
申请号：US893871
申请日：1992-06-05
申请人： Ronald W. Yoder , Ronald E. Lange , William A. Shelly , Russell W. Guenthner , Richard L. Demers
发明人： Ronald W. Yoder , Ronald E. Lange , William A. Shelly , Russell W. Guenthner , Richard L. Demers
IPC分类号： G06F9/26 , G06F9/22
CPC分类号： G06F9/267
摘要： In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.
摘要翻译：为了有效地执行在中央处理单元中执行扩展指令所需的微步骤，提供了具有其自己的定序器的主序列控制器和单独的基本操作控制器以及半自主运行的能力。通常，主序列控制器确定基本操作控制器的操作，但是在执行例如需要扩展基本操作的多字指令的情况下，基本操作控制器暂时控制主控制器，直到扩展基本操作已经完成。结果是相对简单的定序器，其支持紧密的微编码功能，其中许多顺序决定可以被预先确定。

3. 发明授权

US06223228B1 Apparatus for synchronizing multiple processors in a data processing system 有权
标题翻译：用于在数据处理系统中同步多个处理器的装置
公开(公告)号：US06223228B1
公开(公告)日：2001-04-24
申请号：US09156377
申请日：1998-09-17
申请人： Charles P. Ryan , William A. Shelly , Ronald W. Yoder
发明人： Charles P. Ryan , William A. Shelly , Ronald W. Yoder
IPC分类号： G06F112
CPC分类号： G06F9/30087 , G06F1/04 , G06F11/2236 , G06F11/3466
摘要： Two instructions are provided to synchronize multiple processors (92) in a data processing system (80). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (276) to all of the active processors (92) in the system (80). Processors (92) wait for receipt of the synchronize signal (278) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (278) is activated at the next clock cycle after receipt of the interrupt signal (278). An optional timeout value is provided to protect against hanging a waiting processor (92) that misses the interrupt (278). Whenever the WSYNC instruction is activated by receipt of the interrupt (278), a trace is started to trace a fixed number of events to an internal Trace Cache (58).
摘要翻译：提供两个指令以同步数据处理系统（80）中的多个处理器（92）。发送同步指令（TSYNC）向系统（80）中的所有活动处理器（92）发送同步处理器中断（276）。处理器（92）通过执行等待同步（WSYNC）指令等待接收同步信号（278）。等待这种信号（278）的每个处理器在接收到中断信号（278）之后的下一个时钟周期被激活。提供可选的超时值以防止挂起错过中断的等待处理器（92）（278）。每当通过接收到中断（278）激活WSYNC指令时，将启动跟踪以将固定数量的事件跟踪到内部跟踪缓存（58）。

4. 发明授权

US06230263B1 Data processing system processor delay instruction 有权
标题翻译：数据处理系统处理器延时指令
公开(公告)号：US06230263B1
公开(公告)日：2001-05-08
申请号：US09156376
申请日：1998-09-17
申请人： Charles P. Ryan , Ronald W. Yoder , William A. Shelly
发明人： Charles P. Ryan , Ronald W. Yoder , William A. Shelly
IPC分类号： G06F930
CPC分类号： G06F9/30079
摘要： A processor (92) in a data processing system (80) provides a DELAY instruction. Executing the DELAY instruction causes the processor (92) to a specified integral number of clock (98) cycles before continuing. Delays are guaranteed to have a linear relationship with a constant slope with the specified number of clock cycles. Incrementing the specified delay through a range allows exhaustive testing of interactions among multiple processors.
摘要翻译：数据处理系统（80）中的处理器（92）提供DELAY指令。执行DELAY指令使处理器（92）在指定的整数时钟（98）周期之前继续。延迟保证与具有指定时钟周期数的恒定斜率具有线性关系。通过一个范围增加指定的延迟允许对多个处理器之间的交互进行详尽的测试。

5. 发明授权

US06199156B1 System for explicitly referencing a register for its current content when performing processor context switch 有权
标题翻译：用于在执行处理器上下文切换时显式地引用其当前内容的寄存器的系统
公开(公告)号：US06199156B1
公开(公告)日：2001-03-06
申请号：US09212842
申请日：1998-12-16
申请人： Ronald W. Yoder , Lowell McCulley , Russell W. Guenthner
发明人： Ronald W. Yoder , Lowell McCulley , Russell W. Guenthner
IPC分类号： G06F1202
CPC分类号： G06F9/30076 , G06F9/3004 , G06F9/30105 , G06F9/30123 , G06F9/461
摘要： In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by loading the safe store buffer from a safe store stack frame, then delaying loading registers either until actually utilized, or by a background process that loads registers utilizing unused memory cycles. A flag is used for each register that indicates whether the register contents are valid. This flag is cleared for each of the registers whenever such a state transition is made. Then, the flag is set for a register when it is referenced and made valid.
摘要翻译：在包含包含所有寄存器的有效副本的安全存储缓冲器的数据处理系统中，可以通过从安全存储堆栈帧中加载安全存储缓冲区，以更少的周期执行从较高安全程序到较低安全程序的处理器转换，然后延迟加载寄存器直到实际使用，或通过使用未使用的存储器周期加载寄存器的后台进程。每个寄存器都使用一个标志，指示寄存器内容是否有效。每当进行这种状态转换时，这个标志就被清除。然后，当引用标志被设置为一个寄存器并被赋值。

6. 发明授权

US6014757A Fast domain switch and error recovery in a secure CPU architecture 失效
标题翻译：快速域切换和安全CPU架构中的错误恢复
公开(公告)号：US6014757A
公开(公告)日：2000-01-11
申请号：US994476
申请日：1997-12-19
申请人： Ronald W. Yoder , Russell W. Guenthner , Wayne R. Buzby
发明人： Ronald W. Yoder , Russell W. Guenthner , Wayne R. Buzby
IPC分类号： G06F9/38 , G06F11/14 , G06F11/00
CPC分类号： G06F11/1405 , G06F9/3863 , G06F11/1407
摘要： In order to gather, store temporarily and efficiently deliver safestore information in a CPU having data manipulation circuitry including a register bank, first and second serially oriented safestore buffers are employed. At suitable times during the processing of information, a copy of the instantaneous contents of the register bank is transferred into the first safestore buffer. After a brief delay, a copy of the first safestore buffer is transferred into the second safestore buffer. If a call for a domain change (which might include a process change or a fault) is sensed, a safestore frame is sent to cache, and the first safestore buffer is loaded from he second safestore buffer rather than from the register bank. Later, during a climb operation, if a restart of the interrupted process is undertaken and the restoration of the register bank is directed to be taken from the first safestore buffer, this source, rather than the safestore frame stored in cache, is employed to obtain a corresponding increase in the rate of restart. In one embodiment, the transfer of information between the register bank and the safestore buffers is carried out on a bit-by-bit basis to achieve additional flexibility of operation and also to conserve integrated circuit space.
摘要翻译：为了收集，存储在具有包括寄存器组的数据操作电路的CPU中临时且有效地传送保险箱信息，采用第一和第二串行存取缓冲器。在处理信息的适当时候，寄存器组的瞬时内容的副本被传送到第一个保险箱存储缓冲器。经过短暂的延迟后，第一个safestore缓冲区的副本将被传输到第二个safestore缓冲区。如果检测到域更改的呼叫（可能包括进程更改或故障），则将保险箱帧发送到缓存，并且第一个保险箱存储缓冲区从其第二个保险箱存储缓冲区加载，而不是从注册库中加载。之后，在爬升操作期间，如果进行中断处理的重新启动，并且指示从第一个保险箱缓冲器取出寄存器组的恢复，则使用该源而不是存储在高速缓存中的保存存储帧来获得相应地提高了重启速度。在一个实施例中，在寄存器组和保险箱存储缓冲器之间的信息传输是在逐位的基础上进行的，以实现额外的操作灵活性并且还节省集成电路空间。

7. 发明授权

US5905857A Safestore procedure for efficient recovery following a fault during execution of an iterative execution instruction 失效
标题翻译：在执行迭代执行指令时发生故障后进行有效恢复的安全保护程序
公开(公告)号：US5905857A
公开(公告)日：1999-05-18
申请号：US820814
申请日：1997-03-19
申请人： Wayne R. Buzby , Ronald W. Yoder , John E. Wilhite
发明人： Wayne R. Buzby , Ronald W. Yoder , John E. Wilhite
IPC分类号： G06F11/14 , G06F11/30 , G06F11/00
CPC分类号： G06F11/1407
摘要： In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a safestore memory for storing the contents of the plurality of software visible registers, after a data manipulation operation, is provided. Iterative execution instructions subject to a page fault are specially handled in that, during execution, status information indicative of the ongoing status and valid intermediate results are additionally stored in the safestore memory. Then, in the event of a page fault encountered during the execution of the iterative execution instruction, execution is suspended until access to a valid copy of the missing page is obtained. When a valid copy becomes available, the execution of the iterative execution instruction is restarted at the point at which the valid intermediate results had been obtained prior to occurrence of the page fault.
摘要翻译：为了收集，存储临时且有效地在具有包括多个软件可见寄存器的数据操作电路的容错中央处理单元中传送（如果需要的话）存储信息，用于存储多个软件可见寄存器的内容的保存存储器，在提供数据操作操作之后。受到页面错误的迭代执行指令被特别处理，因为在执行期间，指示正在进行的状态和有效的中间结果的状态信息被另外存储在保险箱存储器中。然后，在执行迭代执行指令期间遇到页面错误的情况下，执行被暂停，直到获得缺页的有效副本。当有效的副本可用时，迭代执行指令的执行在页面错误发生之前已经获得有效中间结果的点重新启动。

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