专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06621043B1 Laser trim process control 失效
标题翻译：激光修整过程控制
公开(公告)号：US06621043B1
公开(公告)日：2003-09-16
申请号：US10033061
申请日：2001-11-09
申请人： Don Lambert , Valerie Vivares , Ajit M. Dubey
发明人： Don Lambert , Valerie Vivares , Ajit M. Dubey
IPC分类号： B23K2600
CPC分类号： B23K26/02 , B23K26/702
摘要： A method of calibrating a laser utilized in a laser element cutting system utilizing a mechanical gauge having pairs of metal pads formed in rows and columns on a substrate material. The height of the metal pads varies in each row with each column having the same height. The depth of the substrate material under the metal pads varies. The mechanical gauge is subjected to a laser cut process and the mechanical gauge is illuminated by a light source. The light shining through positions of metal pads indicates that the metal pad and the underlying substrate material have been cut. The depth of cut is determined from the thickness of the metal layer and the thickness of the substrate material that have been cut.
摘要翻译：一种校准在激光元件切割系统中使用的激光的方法，该激光元件切割系统利用在基片材料上以行和列形成的金属片对。金属垫的高度在每一列上变化，每列具有相同的高度。金属焊盘下方的基板材料的深度变化。机械量规经受激光切割过程，机械表由光源照射。通过金属垫的位置照射的光指示金属垫和下面的基底材料已被切割。切割深度由金属层的厚度和已经切割的基材的厚度确定。

2. 发明授权

US06348142B1 Electroplating multi-trace circuit board substrates using single tie bar 有权
标题翻译：电镀多轨电路板基板采用单拉杆
公开(公告)号：US06348142B1
公开(公告)日：2002-02-19
申请号：US09633620
申请日：2000-08-07
申请人： Valerie Vivares , Edwin R. Fontecha
发明人： Valerie Vivares , Edwin R. Fontecha
IPC分类号： C25D502
CPC分类号： H05K3/242 , H01L21/4846 , H01L21/486 , H01L23/498 , H01L24/45 , H01L24/48 , H01L2224/05599 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H05K3/02 , H05K3/027 , H05K2203/095 , H05K2203/107 , H05K2203/1572 , H05K2203/175 , H01L2924/00 , H01L2924/00015 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A method of electroplating circuit board substrate having a high density, multi-trace circuit pattern formed on at least one major surface of an insulative substrate, without requiring formation and at least partial removal of a large plurality of electrically conductive tie bars contacting each of the circuit traces for supplying electroplating potential/current, comprises providing the at least one major surface with a single tie bar having at least a pair of laterally extending arms in simultaneous electrical contact with an end of each trace. Portions of the tie bar extension arms are selectively removed after completion of electroplating, e.g., by laser drilling or plasma etching, to electrically separate each of the circuit traces from the tie bar. According to an embodiment of the invention, electroplating is simultaneously performed on a dual-sided substrate including electrically interconnected circuit patterns formed on opposite sides thereof. The invention enjoys particular utility in the fabrication of ball grid array (BGA) semiconductor device packages.
摘要翻译：一种电镀电路板基板的方法，其具有形成在绝缘基板的至少一个主表面上的高密度多迹线电路图案，而不需要形成并且至少部分地去除大量多个导电连接杆用于提供电镀电位/电流的电路迹线包括向所述至少一个主表面提供具有至少一对横向延伸的臂的单个连接杆，所述至少一个横向延伸臂与每个迹线的端部同时电接触。连接杆延伸臂的部分例如通过激光钻孔或等离子体蚀刻在电镀完成之后被选择性地去除，以使电路迹线与连接条电气分离。根据本发明的实施例，电镀同时在包括形成在其相对侧上的电互连电路图案的双面基板上进行。本发明在球栅阵列（BGA）半导体器件封装的制造中具有特别的用途。

3. 发明授权

US06432291B1 Simultaneous electroplating of both sides of a dual-sided substrate 有权
标题翻译：同时电镀双面基板的两面
公开(公告)号：US06432291B1
公开(公告)日：2002-08-13
申请号：US09641434
申请日：2000-08-18
申请人： Valerie Vivares , Robert Newman , Edwin R. Fontecha
发明人： Valerie Vivares , Robert Newman , Edwin R. Fontecha
IPC分类号： C25D502
CPC分类号： C25D7/12 , H01L21/4846 , H01L2224/32225 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2924/15311 , H05K3/242 , H05K3/28 , H05K2203/0195 , H05K2203/1572 , H01L2924/00014 , H01L2924/00
摘要： A method of simultaneously electroplating both sides of a dual-sided circuit board substrate having electrically connected, multi-trace circuit patterns formed on both sides of the substrate, without requiring formation and at least partial removal of electrically conductive tie bars and associated extensions, comprises steps of simultaneously electrically contacting each feature of a first one of the circuit patterns with a multi-fingered electrical contactor, and applying an electrical potential to the contactor to effect simultaneous electroplating on the circuit patterns on both sides of the substrate. According to an embodiment of the invention, the multi-fingered contactor comprises an array of electrically conductive wires, rods, or filaments extending from one surface of a metal plate. The invention finds particular utility in the fabrication of ball grid array (BGA) semiconductor device packages.
摘要翻译：一种同时电镀双面电路板基板的两面的方法，其具有形成在基板的两侧上的具有电连接的多迹线电路图案，而不需要形成和至少部分去除导电连接条和相关联的延伸部分，包括将电路图案中的第一电路图案的每个特征与多指电接触器同时电接触的步骤，以及向接触器施加电势以对基板两侧的电路图案进行同时电镀。根据本发明的实施例，多指接触器包括从金属板的一个表面延伸的导电线，棒或细丝阵列。本发明在球栅阵列（BGA）半导体器件封装的制造中具有特别的用途。

4. 发明授权

US06426290B1 Electroplating both sides of a workpiece 有权
标题翻译：电镀两面工件
公开(公告)号：US06426290B1
公开(公告)日：2002-07-30
申请号：US09641351
申请日：2000-08-18
申请人： Valerie Vivares , Robert Newman , Edwin R. Fontecha
发明人： Valerie Vivares , Robert Newman , Edwin R. Fontecha
IPC分类号： H01L2144
CPC分类号： H05K3/242 , H01L2224/48227 , H01L2224/48465 , H01L2924/15311 , H05K3/28 , H05K3/321 , H05K2203/0191 , H05K2203/1476 , H05K2203/1572 , H01L2924/00
摘要： A method of electroplating both sides of a dual-sided circuit board substrate having electrically connected, multi-trace circuit patterns formed on both sides of the substrate, without requiring formation and at least partial removal of electrically conductive tie bars, comprises steps of covering and electrically contacting a first one of the circuit patterns with a first layer of electrically conductive material, applying an electrical potential to the first layer of electrically conductive material to effect electroplating on the second one of the circuit patterns, removing the first layer of electrically conductive material, covering and electrically contacting the second one of the circuit patterns with a second layer of electrically conductive material, applying an electrical potential to the second layer of electrically conductive material to effect electroplating on the first one of the circuit patterns, and removing the second layer of electrically conductive material.
摘要翻译：电镀双面电路板基板的两面的方法，其具有形成在基板的两侧上的电连接的多迹线电路图案，而不需要形成和至少部分去除导电连接条，包括以下步骤：将电路图案中的第一个与第一导电材料层电接触，将电位施加到第一导电材料层以在第二电路图案上实现电镀，去除第一层导电材料覆盖和电接触第二电路图案与第二层导电材料，将电位施加到第二层导电材料上以在第一电路图案上实现电镀，以及去除第二层的导电材料。

5. 发明授权

US06319752B1 Single-layer autorouter 有权
标题翻译：单层自动布线器
公开(公告)号：US06319752B1
公开(公告)日：2001-11-20
申请号：US09556304
申请日：2000-04-24
申请人： Alexander Tain , Joan L. Tan , Valerie Vivares
发明人： Alexander Tain , Joan L. Tan , Valerie Vivares
IPC分类号： H01L2144
CPC分类号： H01L24/81 , G06F17/5077 , H01L23/49838 , H01L2224/16225 , H01L2224/81801 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311
摘要： A novel method of automatically routing connections from bumps on a die to package pins in an advanced IC package such as a flip-chip package. The method involves creating graphic presentations of the die having the bumps and the package having pins, and placing the graphic presentation of the die into the graphic presentation of the package. If a netlist identifying interconnections between the bumps and the pins is available, the best route from a bump on the die to a corresponding package pin identified in the netlist is generated in accordance with preset requirements. If the netlist is not available, the best route from the bump to any package pin is generated in accordance with the preset requirements.
摘要翻译：一种将芯片上的凸点连接自动路由到先进的IC封装（如倒装芯片封装）封装引脚的新颖方法。该方法包括创建具有凸块和具有销的封装的裸片的图形呈现，以及将裸片的图形呈现放置在包装的图形呈现中。如果识别凸块和引脚之间的互连的网表可用，则根据预设的要求生成从芯片上的凸块到网表中标识的相应封装引脚的最佳路径。如果网表不可用，则根据预设的要求生成从凸块到任何封装引脚的最佳路径。

6. 发明授权

US06983438B1 Design tool for integrated circuit design 失效
标题翻译：集成电路设计设计工具
公开(公告)号：US06983438B1
公开(公告)日：2006-01-03
申请号：US09643847
申请日：2000-08-23
申请人： Robert Newman , Pranabendra Sarma , Valerie Vivares
发明人： Robert Newman , Pranabendra Sarma , Valerie Vivares
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L24/06 , H01L2224/05553 , H01L2224/06179 , H01L2224/49171 , H01L2924/00011 , H01L2924/14 , H01L2924/00 , H01L2924/01077
摘要： A method and software relating to determining whether a square die fits into a package without generating drawings. Package parameters are defined and used to calculate die characteristics. Calculated die characteristics are compared to defined package parameters and/or to calculated package parameters to make a determination of whether a die with the calculated characteristics fits into a package as defined by its parameters. The method and software allow design of dies to fit packages, the design of packages to fit dies, and simultaneous design of dies and packages that fit one another.
摘要翻译：一种方法和软件，用于确定方形裸片是否适合于包装而不产生图纸。定义包装参数并用于计算模具特性。将计算的管芯特性与定义的包装参数和/或计算的包装参数进行比较，以确定具有计算特征的管芯是否符合其参数所定义的包装。该方法和软件允许设计模具以适应包装，设计适合模具的包装，以及同时设计适合彼此的模具和包装。

7. 发明授权

US06569694B1 Method of checking BGA substrate design 有权
标题翻译：检查BGA基板设计的方法
公开(公告)号：US06569694B1
公开(公告)日：2003-05-27
申请号：US09892799
申请日：2001-06-28
申请人： Pranabendra Sarma , Alexander Tain , Valerie Vivares
发明人： Pranabendra Sarma , Alexander Tain , Valerie Vivares
IPC分类号： H01L2166
CPC分类号： G06F17/5081 , H01L23/3677 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48464 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： A novel method is provided for checking BGA substrate design made using an APD design tool. User's netlist containing information on a die to be mounted on the BGA substrate is entered into an interface software system providing an interface to the APD design tool. The interface software system extracts the design netlist generated from the APD design of the BGA substrate, and compares this netlist to the user's netlist. If no differences are reported, the BGA substrate design is considered to be correct.
摘要翻译：提供了一种用于检查使用APD设计工具制作的BGA衬底设计的新颖方法。用于将要安装在BGA基板上的芯片上的信息的用户网表输入到提供APD设计工具接口的接口软件系统中。接口软件系统提取从BGA基板的APD设计生成的设计网表，并将该网表与用户的网表进行比较。如果没有报告差异，则认为BGA衬底设计是正确的。

8. 发明授权

US06515354B1 Micro-BGA beam lead connection with cantilevered beam leads 有权
标题翻译：微BGA光束引线与悬臂梁引线连接
公开(公告)号：US06515354B1
公开(公告)日：2003-02-04
申请号：US09643848
申请日：2000-08-23
申请人： Edwin R. Fontecha , Viswanath Valluri , Valerie Vivares
发明人： Edwin R. Fontecha , Viswanath Valluri , Valerie Vivares
IPC分类号： H01L23495
CPC分类号： H01L23/4985 , H01L2924/0002 , H01L2924/00
摘要： A tape automated bonding (TAB) tape is provided with an insulating tape having a die receiving section. The TAB tape also has a conductive wiring pattern forming a plurality of traces including a land at one end and a beam lead at another end. A tape window is formed in a portion of the tape die receiving section. At least one trace beam lead extends over the tape window from a first direction and is connected to a tie bar adjacent an opposing side of the tape window and at least one trace beam lead extends over the tape window from a second direction different than the first direction and is cantilevered over the tape window.
摘要翻译：带式自动接合（TAB）带设置有具有管芯接收部分的绝缘带。 TAB带还具有导电布线图案，该导电布线图形形成多个迹线，其包括在一端处的台脊和另一端的光束引线。磁带窗口形成在磁带模接收部分的一部分中。至少一个跟踪光束引线从第一方向延伸到磁带窗口上方并且连接到与磁带窗口的相对侧相邻的连接杆，并且至少一个轨迹引线从不同于第一方向的第二方向延伸到磁带窗口上方方向，并悬挂在磁带窗口上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式