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1. 发明授权

US06627940B1 Memory cell arrangement 失效
标题翻译：存储单元布置
公开(公告)号：US06627940B1
公开(公告)日：2003-09-30
申请号：US09937838
申请日：2002-02-05
申请人： Dirk Schumann , Bernhard Sell , Hans Reisinger , Josef Willer
发明人： Dirk Schumann , Bernhard Sell , Hans Reisinger , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823
摘要： A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.
摘要翻译：存储单元阵列包括形成平行的第一和第二沟槽的衬底。晶体管的上部源极/漏极区域邻接第一和第二个第二沟槽中的两个，并且位于其下部源极/漏极区域的上方。与晶体管相关联的第一沟槽中的导电结构在其第一边缘邻接上部源极/漏极区。相关联的第一沟槽中的绝缘结构将导电结构与相关联的第一沟槽的第二边缘和底部绝缘。在其上是另一个绝缘层的字线在上部/源极漏极区域上方并且平行于相关联的第一沟槽凸起进入第二沟槽。绝缘空间横向与字线连接。导电结构上的与上部源极/漏极区域电连通的触点与电容器连接。

2. 发明授权

US06548350B2 Method of fabricating an integrated circuit configuration with at least one capacitor 有权
公开(公告)号：US06548350B2
公开(公告)日：2003-04-15
申请号：US10093039
申请日：2002-03-07
申请人： Bernhard Sell , Dirk Schumann , Josef Willer
发明人： Bernhard Sell , Dirk Schumann , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L27/10852
摘要： The capacitor is arranged on the surface of a substrate. A first capacitor electrode has a middle part and a side part, which point vertically upwards, are arranged beside each other and are connected with each other via an upper part located above said middle part and said side part. The middle part is longer than the side part and is connected with other components of the circuit configuration located below said middle part and said side part. The first capacitor electrode is provided with a capacitor dielectric. A second capacitor electrode borders the capacitor dielectric.

3. 发明授权

US06525363B1 Integrated circuit configuration with at least one capacitor and method for producing the same 有权
标题翻译：具有至少一个电容器的集成电路配置及其制造方法
公开(公告)号：US06525363B1
公开(公告)日：2003-02-25
申请号：US09677433
申请日：2000-10-02
申请人： Josef Willer , Bernhard Sell , Dirk Schumann
发明人： Josef Willer , Bernhard Sell , Dirk Schumann
IPC分类号： H01L27108
CPC分类号： H01L28/84 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L28/86 , H01L28/90
摘要： A first capacitor electrode of the capacitor, which is arranged on a surface of a substrate (1), has a lower part (T) and a lateral part (S) arranged thereon. At least a first lateral area of the lateral part (S) is undulatory in such a way that it has bulges and indentations alternately which are formed along lines each running in a plane parallel to the surface of the substrate (1). The lateral part (T) can be produced by depositing conductive material in a depression (V) which is produced in a layer sequence whose layers are composed alternately of a first material and a second material and in which the first material is subjected to wet etching selectively with respect to the second material down to a first depth. The first capacitor electrode is provided with a capacitor dielectric (KD). A second capacitor electrode (P) adjoins the capacitor dielectric (KD).
摘要翻译：设置在基板（1）的表面上的电容器的第一电容电极具有布置在其上的下部（T）和侧部（S）。横向部分（S）的至少第一横向区域以这样的方式波动，使得其具有沿着平行于基底（1）的表面的平面中的每条线条沿着线形成的凸起和凹陷。横向部分（T）可以通过将导电材料沉积在层中产生的凹陷（V）中来制造，层的顺序是层，其层由第一材料和第二材料交替组成，并且其中第一材料经受湿蚀刻相对于第二材料选择性地到达第一深度。第一电容器电极设置有电容器电介质（KD）。第二电容器电极（P）与电容器电介质（KD）相邻。

4. 发明授权

US06504200B2 DRAM cell configuration and fabrication method 有权
公开(公告)号：US06504200B2
公开(公告)日：2003-01-07
申请号：US09951243
申请日：2001-09-12
申请人： Till Schlösser , Bernhard Sell , Josef Willer
发明人： Till Schlösser , Bernhard Sell , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823
摘要： Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.

5. 发明授权

US06800898B2 Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors 失效
标题翻译：集成电路结构和制造具有掩埋位线或沟槽电容器的电容结构的方法
公开(公告)号：US06800898B2
公开(公告)日：2004-10-05
申请号：US09951239
申请日：2001-09-12
申请人： Annalisa Cappelani , Bernhard Sell , Josef Willer
发明人： Annalisa Cappelani , Bernhard Sell , Josef Willer
IPC分类号： H01L2976
CPC分类号： H01L27/10844 , H01L27/10861 , H01L27/10876
摘要： The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.
摘要翻译：形成在基板中的凹部的下部的底部和侧面具有绝缘结构。第一导电类型的导电结构的第一部分位于凹部的下部。低于第一类型的第二导电类型的导电结构的第二部分位于上部并且在凹部的侧面与基板的区域相邻。导电结构在其第一和第二部分之间具有扩散阻挡层。导电结构被配置为具有垂直晶体管的DRAM单元配置的位线，由此S / Du表示下源极/漏极区域，S / Do表示连接到存储电容器的上部源极/漏极区域。或者，导电结构被配置为存储电容器，并且上部源极漏极/区域连接到位线。

6. 发明申请

US20060073659A1 Method for fabricating a storage capacitor 审中-公开
标题翻译：存储电容器的制造方法
公开(公告)号：US20060073659A1
公开(公告)日：2006-04-06
申请号：US11285639
申请日：2005-11-22
申请人： Bernhard Sell , Annette Sanger , Dirk Schumann
发明人： Bernhard Sell , Annette Sanger , Dirk Schumann
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/02164 , H01L21/0217 , H01L21/02271 , H01L21/28518 , H01L21/31604 , H01L27/10814 , H01L28/60
摘要： The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.
摘要翻译：本发明涉及一种用于制造设计为沟槽或层叠电容器的存储电容器的新颖方法，特别用于DRAM存储单元。该方法包括形成下部金属电容器电极，存储电介质和上部电容器电极的步骤。下部金属电容器电极以自对准的方式形成在硅基材上，使得首先在将形成下电容器电极的位置处产生未覆盖的硅区域，然后选择性地形成金属硅化物未覆盖的硅区域。

7. 发明授权

US06998307B2 Method for fabricating a storage capacitor 失效
公开(公告)号：US06998307B2
公开(公告)日：2006-02-14
申请号：US10650055
申请日：2003-08-26
申请人： Bernhard Sell , Annette Sänger , Dirk Schumann
发明人： Bernhard Sell , Annette Sänger , Dirk Schumann
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/28518 , H01L21/31604 , H01L27/10814 , H01L28/60
摘要： The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

8. 发明授权

US06620724B1 Low resistivity deep trench fill for DRAM and EDRAM applications 有权
标题翻译：用于DRAM和EDRAM应用的低电阻深沟槽填充
公开(公告)号：US06620724B1
公开(公告)日：2003-09-16
申请号：US10142518
申请日：2002-05-09
申请人： Uwe Schroeder , Helmut Horst Tews , Irene McStay , Manfred Hauf , Matthias Goldbach , Bernhard Sell , Harald Seidl , Dirk Schumann , Rajarao Jammy , Joseph F. Shepard, Jr. , Jean-Marc Rousseau
发明人： Uwe Schroeder , Helmut Horst Tews , Irene McStay , Manfred Hauf , Matthias Goldbach , Bernhard Sell , Harald Seidl , Dirk Schumann , Rajarao Jammy , Joseph F. Shepard, Jr. , Jean-Marc Rousseau
IPC分类号： H01L214763
CPC分类号： H01L28/60 , H01L27/10861
摘要： Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.
摘要翻译：提供其具有低电阻率的具有低填充材料的深沟槽的半导体器件以及制造这种半导体器件的方法。

9. 发明授权

US06987295B2 Trench capacitor and method for fabricating the trench capacitor 失效
标题翻译：沟槽电容器和制造沟槽电容器的方法
公开(公告)号：US06987295B2
公开(公告)日：2006-01-17
申请号：US10650817
申请日：2003-08-28
申请人： Bernhard Sell , Annette Sänger , Dirk Schumann
发明人： Bernhard Sell , Annette Sänger , Dirk Schumann
IPC分类号： H01L27/108
CPC分类号： H01L27/10861 , H01L27/1203
摘要： A trench capacitor for use in a DRAM memory cell contains a lower capacitor electrode, a storage dielectric, and an upper capacitor electrode, which are at least partially disposed in a trench. The lower capacitor electrode adjoins, in a lower trench region, a wall of the trench, while in the upper trench region there is a spacer layer that adjoins a wall of the trench and is made from an insulating material. The upper electrode contains at least three layers, a first layer disposed in the trench on the storage dielectric and containing doped polysilicon, a second layer disposed on the first layer and containing metal-silicide, and a third layer disposed on the second layer and containing doped polysilicon. The layers of the upper electrode in each case extending along the walls and the base of the trench up to at least the upper edge of the spacer layer.
摘要翻译：用于DRAM存储单元的沟槽电容器包括至少部分地设置在沟槽中的下电容器电极，存储电介质和上电容器电极。下部电容器电极在下部沟槽区域中邻接沟槽的壁，而在上部沟槽区域中存在间隔层，该间隔层邻接沟槽的壁并由绝缘材料制成。上电极包含至少三层，第一层设置在存储电介质上的沟槽中并含有掺杂多晶硅，第二层设置在第一层上并含有金属硅化物，第三层设置在第二层上并含有掺杂多晶硅。每个壳体中的上电极的层沿着沟槽的壁和基底延伸到至少间隔层的上边缘。

10. 发明授权

US08941214B2 Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width 有权
标题翻译：具有颈缩半导体本体的半导体器件和形成宽度不同的半导体器件的方法
公开(公告)号：US08941214B2
公开(公告)日：2015-01-27
申请号：US13995634
申请日：2011-12-22
申请人： Bernhard Sell
发明人： Bernhard Sell
IPC分类号： H01L29/06 , H01L21/02 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/02532 , H01L21/30604 , H01L21/3083 , H01L21/823412 , H01L29/0657 , H01L29/0847 , H01L29/1037 , H01L29/16 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/66795 , H01L29/6681 , H01L29/66818 , H01L29/785 , H01L29/7851 , H01L29/7853
摘要： Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
摘要翻译：描述了半导体器件的半导体器件和形成具有不同宽度的半导体器件的方法。例如，半导体器件包括设置在衬底上方的半导体本体。栅电极堆叠设置在半导体本体的一部分上，以在栅电极堆叠下方限定半导体本体中的沟道区。源极和漏极区域限定在栅电极堆叠的任一侧上的半导体本体中。侧壁间隔件邻近栅极电极堆叠并且仅在源极和漏极区域的一部分上设置。侧壁间隔物下方的源区和漏区的部分具有高于半导体本体的沟道区的高度和宽度的高度和宽度。

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