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1. 发明授权

US06800898B2 Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors 失效
标题翻译：集成电路结构和制造具有掩埋位线或沟槽电容器的电容结构的方法
公开(公告)号：US06800898B2
公开(公告)日：2004-10-05
申请号：US09951239
申请日：2001-09-12
申请人： Annalisa Cappelani , Bernhard Sell , Josef Willer
发明人： Annalisa Cappelani , Bernhard Sell , Josef Willer
IPC分类号： H01L2976
CPC分类号： H01L27/10844 , H01L27/10861 , H01L27/10876
摘要： The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.
摘要翻译：形成在基板中的凹部的下部的底部和侧面具有绝缘结构。第一导电类型的导电结构的第一部分位于凹部的下部。低于第一类型的第二导电类型的导电结构的第二部分位于上部并且在凹部的侧面与基板的区域相邻。导电结构在其第一和第二部分之间具有扩散阻挡层。导电结构被配置为具有垂直晶体管的DRAM单元配置的位线，由此S / Du表示下源极/漏极区域，S / Do表示连接到存储电容器的上部源极/漏极区域。或者，导电结构被配置为存储电容器，并且上部源极漏极/区域连接到位线。

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