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    • 1. 发明授权
    • Multiple-mode compensated buffer circuit
    • 多模式补偿缓冲电路
    • US07642807B2
    • 2010-01-05
    • US11768496
    • 2007-06-26
    • Dipankar BhattacharyaGregg R. HarlemanMakeshwar KothandaramanJohn C. KrizBernard L. Morris
    • Dipankar BhattacharyaGregg R. HarlemanMakeshwar KothandaramanJohn C. KrizBernard L. Morris
    • H03K17/16
    • H03K19/00376
    • A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.
    • 以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器,每个预驱动器具有连接到相应一个输出块的输入的输出。 输出块的各输出端连接在一起形成缓冲电路的输出。 输出块按顺序排列并且被二进制加权,使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。 每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。 提供给预驱动器的各个控制信号共同表示二进制码字,第二模式中的二进制码字等效于第一模式中的二进制码字的算术移位。
    • 4. 发明授权
    • Electrostatic discharge protection circuit
    • 静电放电保护电路
    • US08089739B2
    • 2012-01-03
    • US12438460
    • 2007-10-30
    • Dipankar BhattacharyaMakeshwar KothandaramanJohn C. KrizBernard L. MorrisYehuda Smooha
    • Dipankar BhattacharyaMakeshwar KothandaramanJohn C. KrizBernard L. MorrisYehuda Smooha
    • H02H3/22H02H3/20H02H9/04
    • H01L27/0266
    • An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.
    • ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器,以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。 第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。 第二电压供应节点可操作以接收小于第一电压的第二电压。 第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值,并且第二电压钳位器用于将第二电压钳位在第二电压 在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。
    • 5. 发明授权
    • Circuit having enhanced input signal range
    • 电路具有增强的输入信号范围
    • US07432762B2
    • 2008-10-07
    • US11393171
    • 2006-03-30
    • Dipankar BhattacharyaMakeshwar KothandaramanJohn C. KrizBernard L. Morris
    • Dipankar BhattacharyaMakeshwar KothandaramanJohn C. KrizBernard L. Morris
    • H03F3/45G06G7/12
    • H03F3/45183H03F2200/513H03F2200/78H03F2203/45314H03F2203/45361H03F2203/45552H03F2203/45684
    • A circuit having an enhanced input signal range includes a differential amplifier operative to receive at least first and second signals and to generate a difference signal at an output thereof which is a function of the difference between the first and second signals. The differential amplifier includes an input stage having at least first and second transistors having a first threshold voltage associated therewith and being operative to receive the first and second signals, respectively, and a load including at least third and fourth transistors having a second threshold voltage associated therewith, the first threshold voltage being greater than the second threshold voltage. The circuit further includes an output stage coupled to the differential amplifier and operative to receive the difference signal and to generate an output signal of the circuit that is indicative of the difference signal and is referenced to the supply voltage of the circuit.
    • 具有增强的输入信号范围的电路包括差分放大器,其操作以接收至少第一和第二信号,并在其输出处产生作为第一和第二信号之间的差的函数的差分信号。 差分放大器包括具有至少第一和第二晶体管的输入级,其具有与其相关联的第一阈值电压,并且可分别接收第一和第二信号,并且负载包括至少第三和第四晶体管,其具有第二阈值电压相关联 因此,第一阈值电压大于第二阈值电压。 电路还包括耦合到差分放大器的输出级并且可操作地接收差分信号并产生指示差分信号的电路的输出信号并且参考电路的电源电压。
    • 7. 发明授权
    • Buffer circuit with enhanced overvoltage protection
    • 具有增强型过压保护功能的缓冲电路
    • US07430100B2
    • 2008-09-30
    • US11169139
    • 2005-06-28
    • Dipankar BhattacharyaMakeshwar KothandaramanJohn C. KrizBernard L. Morris
    • Dipankar BhattacharyaMakeshwar KothandaramanJohn C. KrizBernard L. Morris
    • H02H3/20
    • H03K19/00315H03K2217/0018
    • A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.
    • 具有增强的过电压保护的缓冲电路包括可耦合到具有第一电压电平的第一电压源的核心缓冲电路。 核心缓冲器电路被配置为接收第一信号并产生作为第一信号的函数的第二信号。 缓冲电路还包括耦合在核心缓冲器电路和信号焊盘之间的保护电路。 保护电路是可操作的:(i)当在信号焊盘处接收的第三信号超过第一电压电平达到第一量值时,将第一信号钳位到约第一电压电平; 和(ii)当第三信号小于或基本上等于第一电压电平时,产生基本上等于第三信号的第一信号。