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1. 发明授权

US07642807B2 Multiple-mode compensated buffer circuit 有权
标题翻译：多模式补偿缓冲电路
公开(公告)号：US07642807B2
公开(公告)日：2010-01-05
申请号：US11768496
申请日：2007-06-26
申请人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03K17/16
CPC分类号： H03K19/00376
摘要： A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.
摘要翻译：以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器，每个预驱动器具有连接到相应一个输出块的输入的输出。输出块的各输出端连接在一起形成缓冲电路的输出。输出块按顺序排列并且被二进制加权，使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。提供给预驱动器的各个控制信号共同表示二进制码字，第二模式中的二进制码字等效于第一模式中的二进制码字的算术移位。

2. 发明申请

US20090002017A1 Multiple-Mode Compensated Buffer Circuit 有权
标题翻译：多模式补偿缓冲电路
公开(公告)号：US20090002017A1
公开(公告)日：2009-01-01
申请号：US11768496
申请日：2007-06-26
申请人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Gregg R. Harleman , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03K19/0175 , H03K19/02
CPC分类号： H03K19/00376
摘要： A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.
摘要翻译：以至少第一模式和第二模式之一工作的补偿缓冲器电路包括多个输出块和多个预驱动器，每个预驱动器具有连接到相应一个输出块的输入的输出。输出块的各输出端连接在一起形成缓冲电路的输出。输出块按顺序排列并且被二进制加权，使得给定的一个输出块的驱动强度大约是在给定输出块之前的输出块的驱动强度的两倍。每个预驱动器根据提供给预驱动器的控制信号选择性地使连接到其上的相应输出块能够补偿用于缓冲电路可能经受的PVT变化的缓冲电路。提供给预驱动器的各个控制信号共同表示二进制码字，第二模式中的二进制码字等价于第一模式中的二进制码字的算术移位。

3. 发明申请

US20080074171A1 Method and Apparatus for Improving Reliability of an Integrated Circuit Having Multiple Power Domains 有权
标题翻译：提高具有多个电源域的集成电路的可靠性的方法和装置
公开(公告)号：US20080074171A1
公开(公告)日：2008-03-27
申请号：US11535198
申请日：2006-09-26
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , H01L27/0251 , H03K19/00315
摘要： An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.
摘要翻译：具有改进的可靠性的IC至少包括第一和第二电路块以及至少第一和第二电力域，第一电路块连接到第一电力域，第二电路块连接到第二电力域。 IC还包括被配置为产生至少第一和第二控制信号的至少一个控制电路。第一控制信号用于选择性地将第一功率域连接到第一电压源，并且第二控制信号用于选择性地将第二功率域连接到第二电压源。 IC包括至少第一和第二钳位电路，第一钳位电路连接到第一电源域，第二钳位电路连接到第二电源域。每个钳位电路可操作以防止相应功率域上的电压升高到对应功率域的规定电压电平以上。

4. 发明授权

US07276957B2 Floating well circuit having enhanced latch-up performance 失效
标题翻译：具有增强的闭锁性能的浮动井回路
公开(公告)号：US07276957B2
公开(公告)日：2007-10-02
申请号：US11239840
申请日：2005-09-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Duane J. Loeper , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Duane J. Loeper , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03K
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.
摘要翻译：用于限定其中形成有至少一个金属氧化物半导体器件的浮动阱的电压电位的电路包括感测电路，其可操作以检测浮动阱连接到的节点处的电压，并产生指示性的控制信号节点处的电压是否基本上在电压范围内。电压范围的较低值基本上等于低于电路的第一电源电压的阈值电压。电压范围的较高值基本上等于高于第一电源电压的阈值电压。用于定义浮动阱的电压电位的电路还包括电压发生器电路，其操作以接收控制信号并产生用于响应于控制信号设置阱的电压电位的偏置信号，偏置信号被控制在整个电压范围。

5. 发明授权

US08089739B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08089739B2
公开(公告)日：2012-01-03
申请号：US12438460
申请日：2007-10-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H3/22 , H02H3/20 , H02H9/04
CPC分类号： H01L27/0266
摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.
摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。第二电压供应节点可操作以接收小于第一电压的第二电压。第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。

6. 发明授权

US07432762B2 Circuit having enhanced input signal range 有权
标题翻译：电路具有增强的输入信号范围
公开(公告)号：US07432762B2
公开(公告)日：2008-10-07
申请号：US11393171
申请日：2006-03-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03F3/45 , G06G7/12
CPC分类号： H03F3/45183 , H03F2200/513 , H03F2200/78 , H03F2203/45314 , H03F2203/45361 , H03F2203/45552 , H03F2203/45684
摘要： A circuit having an enhanced input signal range includes a differential amplifier operative to receive at least first and second signals and to generate a difference signal at an output thereof which is a function of the difference between the first and second signals. The differential amplifier includes an input stage having at least first and second transistors having a first threshold voltage associated therewith and being operative to receive the first and second signals, respectively, and a load including at least third and fourth transistors having a second threshold voltage associated therewith, the first threshold voltage being greater than the second threshold voltage. The circuit further includes an output stage coupled to the differential amplifier and operative to receive the difference signal and to generate an output signal of the circuit that is indicative of the difference signal and is referenced to the supply voltage of the circuit.
摘要翻译：具有增强的输入信号范围的电路包括差分放大器，其操作以接收至少第一和第二信号，并在其输出处产生作为第一和第二信号之间的差的函数的差分信号。差分放大器包括具有至少第一和第二晶体管的输入级，其具有与其相关联的第一阈值电压，并且可分别接收第一和第二信号，并且负载包括至少第三和第四晶体管，其具有第二阈值电压相关联因此，第一阈值电压大于第二阈值电压。电路还包括耦合到差分放大器的输出级并且可操作地接收差分信号并产生指示差分信号的电路的输出信号并且参考电路的电源电压。

7. 发明申请

US20080238399A1 Buffer Circuit Having Multiplexed Voltage Level Translation 有权
标题翻译：具有复用电压电平转换的缓冲电路
公开(公告)号：US20080238399A1
公开(公告)日：2008-10-02
申请号：US11691590
申请日：2007-03-27
申请人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Carol A. Huber , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： G05F5/00
CPC分类号： H03K19/017581 , H03K19/01759
摘要： A buffer circuit is selectively operative in one of at least a first mode and a second mode as a function of a first control signal supplied to the buffer circuit. The buffer circuit includes interface circuitry operative to receive at least second and third control signals referenced to a first voltage level, and to generate an output signal referenced to a second voltage level, the second voltage level being greater than the first voltage level. The output signal is a function of the second control signal in the first mode and is a function of the third control signal in the second mode. The buffer circuit further includes at least first and second circuit portions coupled to the interface circuitry, each of the first and second circuit portions including at least one control input operative to receive the output signal generated by the interface circuitry.
摘要翻译：作为提供给缓冲电路的第一控制信号的函数，缓冲器电路有选择地以至少第一模式和第二模式中的至少一个工作。缓冲电路包括接口电路，其操作以接收参考第一电压电平的至少第二和第三控制信号，并产生参考第二电压电平的输出信号，第二电压电平大于第一电压电平。输出信号是第一模式中的第二控制信号的函数，并且是第二模式中的第三控制信号的函数。缓冲电路还包括耦合到接口电路的至少第一和第二电路部分，第一和第二电路部分中的每一个包括至少一个控制输入，其操作以接收由接口电路产生的输出信号。

8. 发明授权

US07430100B2 Buffer circuit with enhanced overvoltage protection 有权
标题翻译：具有增强型过压保护功能的缓冲电路
公开(公告)号：US07430100B2
公开(公告)日：2008-09-30
申请号：US11169139
申请日：2005-06-28
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H02H3/20
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.
摘要翻译：具有增强的过电压保护的缓冲电路包括可耦合到具有第一电压电平的第一电压源的核心缓冲电路。核心缓冲器电路被配置为接收第一信号并产生作为第一信号的函数的第二信号。缓冲电路还包括耦合在核心缓冲器电路和信号焊盘之间的保护电路。保护电路是可操作的：（i）当在信号焊盘处接收的第三信号超过第一电压电平达到第一量值时，将第一信号钳位到约第一电压电平; 和（ii）当第三信号小于或基本上等于第一电压电平时，产生基本上等于第三信号的第一信号。

9. 发明授权

US07248079B2 Differential buffer circuit with reduced output common mode variation 失效
公开(公告)号：US07248079B2
公开(公告)日：2007-07-24
申请号：US11285800
申请日：2005-11-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris
IPC分类号： H03K19/0175
CPC分类号： H04L25/0276
摘要： A differential buffer circuit includes a current source, a current sink, and a switching circuit connected to the current source at a first node and connected to the current sink at a second node. The switching circuit is operative to selectively control a direction of current flowing through differential outputs of the buffer circuit in response to at least a first control signal. The buffer circuit further includes a common mode detection circuit and a common mode control circuit. The common mode detection circuit is operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage. The common mode control circuit includes a first terminal connected to the current source and a second terminal connected to the current sink. The common mode control circuit is operative to selectively control the output common mode voltage of the buffer circuit as a function of the second control signal.

10. 发明授权

US07145364B2 Self-bypassing voltage level translator circuit 有权
标题翻译：自我旁路电压电平转换电路
公开(公告)号：US07145364B2
公开(公告)日：2006-12-05
申请号：US11065785
申请日：2005-02-25
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K3/012 , H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.
摘要翻译：响应于控制信号，电压电平转换器电路可选择性地以至少两种模式之一工作。在第一模式中，电压电平转换器电路用于将提供第一电压的参考第一源的输入信号转换为参考提供第二电压的第二源的输出信号。在第二模式中，电压电平转换器电路用于提供从电压转换器电路的输入到其输出的信号路径，而不转换输入信号。控制信号表示第一电压和第二电压之间的差。

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