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1. 发明授权

US07180135B1 Double gate (DG) SOI ratioed logic with intrinsically on symmetric DG-MOSFET load 失效
标题翻译：双栅（DG）SOI比率逻辑本质上对称DG-MOSFET负载
公开(公告)号：US07180135B1
公开(公告)日：2007-02-20
申请号：US10951695
申请日：2004-09-29
申请人： Dimitris E. Ioannou , Souvick Mitra , Akram Salman
发明人： Dimitris E. Ioannou , Souvick Mitra , Akram Salman
IPC分类号： H01L27/01
CPC分类号： H01L29/78648 , H01L27/1203
摘要： Disclosed is a Silicon-On-Insulator (SOI) Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) logic family composed of ratioed logic with intrinsically “on” symmetric fully depleted double-gate (DG) SOI MOSFET load(s) and asymmetric fully depleted double gate MOSFET driver(s).
摘要翻译：公开了一种由本质上“对称”全耗尽双栅极（DG）SOI MOSFET负载和不对称的比例逻辑组成的绝缘体上硅绝缘体（SOI）金属氧化物半导体场效应晶体管（MOSFET）逻辑系列完全耗尽的双栅极MOSFET驱动器。

2. 发明授权

US09435841B2 Integrated circuit protection during high-current ESD testing 有权
标题翻译：在大电流ESD测试期间集成电路保护
公开(公告)号：US09435841B2
公开(公告)日：2016-09-06
申请号：US13446394
申请日：2012-04-13
申请人： Shunhua Chang , James Paul Di Sarro , Robert J. Gauthier, Jr. , Nathan Jack , Souvick Mitra
发明人： Shunhua Chang , James Paul Di Sarro , Robert J. Gauthier, Jr. , Nathan Jack , Souvick Mitra
IPC分类号： H02H9/00 , G01R31/00 , H02H9/04 , G01R31/28 , H01L27/02 , H05K9/00
CPC分类号： G01R31/002 , G01R31/2851 , H01L27/0248 , H02H9/046 , H05K9/0067
摘要： A method of protecting devices within an integrated circuit during electro-static discharge (ESD) testing using an ESD test system is provided. The method includes applying a direct current (DC) bias voltage to an input of at least one device of the integrated circuit and applying an ESD simulated signal to at least one other input of the integrated circuit. The applied ESD simulated signal is conducted along a first current path to a first ground, while a low-current signal associated with the at least one device is conducted along a second current path to the second ground. The DC bias voltage is maintained between the input of the at least one device and the second ground at a substantially constant value in response to a signal variation on the second ground that results from the applied ESD simulated signal.
摘要翻译：提供了使用ESD测试系统在静电放电（ESD）测试期间保护集成电路内的器件的方法。该方法包括将直流（DC）偏置电压施加到集成电路的至少一个器件的输入，并将ESD仿真信号施加到集成电路的至少一个其他输入。施加的ESD模拟信号沿着第一电流路径传导到第一地，而与至少一个装置相关联的低电流信号沿着第二电流路径传导到第二地。响应于由所施加的ESD模拟信号产生的第二接地上的信号变化，DC偏置电压在至少一个器件的输入和第二接地之间以基本恒定的值保持。

3. 发明授权

US08686508B2 Structures, methods and applications for electrical pulse anneal processes 失效
标题翻译：电脉冲退火工艺的结构，方法和应用
公开(公告)号：US08686508B2
公开(公告)日：2014-04-01
申请号：US12553523
申请日：2009-09-03
申请人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Robert Robison
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Robert Robison
IPC分类号： H01L23/62
CPC分类号： H01L21/324 , H01L27/0255 , H01L29/8611 , H01L29/866
摘要： Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
摘要翻译：为纳秒电脉冲退火工艺提供了结构和方法。形成静电放电（ESD）N + / P +结构的方法包括在衬底上形成N +扩散，并在衬底上形成P +扩散。 P +扩散与N +扩散电接触。该方法还包括在N +扩散和P +扩散之间形成器件。退火结构或材料的方法包括跨多个纳秒的静电放电（ESD）N + / P +结构施加电脉冲。

4. 发明授权

US08390068B2 Electrostatic discharge protection device and method of fabricating same 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US08390068B2
公开(公告)日：2013-03-05
申请号：US13361051
申请日：2012-01-30
申请人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier, Jr. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L27/01 , H01L29/74 , H01L23/62
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：包括硅控制整流器的集成电路的硅控制整流器和静电放电保护装置。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

5. 发明申请

US20090206367A1 Design Structure and Method for a Silicon Controlled Rectifier (SCR) Structure for SOI Technology 有权
标题翻译：用于SOI技术的硅控整流器（SCR）结构的设计结构和方法
公开(公告)号：US20090206367A1
公开(公告)日：2009-08-20
申请号：US12031084
申请日：2008-02-14
申请人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra
发明人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra
IPC分类号： H01L29/74 , H01L21/332
CPC分类号： H01L29/7436 , H01L27/0259 , H01L29/861
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括一个P + -N体二极管和一个N + -P体二极管。 P + -N体二极管和N + -P体二极管横向集成。

6. 发明申请

US20090108289A1 DESIGN STRUCTURE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE 有权
标题翻译：具有可调触发电压的多功能半导体器件的均匀触发设计结构
公开(公告)号：US20090108289A1
公开(公告)日：2009-04-30
申请号：US11931517
申请日：2007-10-31
申请人： Michel J. Abou-Khalil , Robert Gauthier , Hongmei Li , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Michel J. Abou-Khalil , Robert Gauthier , Hongmei Li , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H01L27/06
CPC分类号： H01L27/0266 , H01L27/0259 , H01L27/0727 , H01L27/0817
摘要： A design structure for a circuit providing the same trigger voltage across the multiple fingers is provided, which comprises a data representing an external current injection source connected to individual fingers of a multi-finger semiconductor device. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source is adjusted so that each finger has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.
摘要翻译：提供了一种用于跨多个指状物提供相同触发电压的电路的设计结构，其包括表示连接到多指半导体器件的各个指状物的外部电流注入源的数据。例如，外部注入电流被提供给MOSFET的主体或晶闸管的栅极。调整来自每个外部电流注入源的供给电流的大小，使得每个手指具有相同的触发电压。外部电流供应电路可以包括二极管或RC触发MOSFET。可以调谐外部电流供应电路的组件以实现多指半导体器件的所有指状物上期望的预定触发电压。

7. 发明授权

US07518845B2 RC-triggered power clamp suppressing negative mode electrostatic discharge stress 失效
标题翻译： RC触发功率钳位抑制负模式静电放电应力
公开(公告)号：US07518845B2
公开(公告)日：2009-04-14
申请号：US11422608
申请日：2006-06-07
申请人： Robert J. Gauthier, Jr. , Dimitrios K. Kontos , Junjun Li , Souvick Mitra , Christopher S. Putnam
发明人： Robert J. Gauthier, Jr. , Dimitrios K. Kontos , Junjun Li , Souvick Mitra , Christopher S. Putnam
IPC分类号： H02H9/00 , H02H1/00
CPC分类号： H02H9/046
摘要： An electrostatic discharge (ESD) power clamp circuit including a RC-delay element coupled to a plurality of serialized inverter elements with a power clamp element and an ESD-triggered keeper device coupled to the plurality of inverters. During negative mode ESD events, the ESD-triggered keeper device is activated and assists the power clamp element to pull up and strongly conduct current to protect the circuit. Additionally, a method of ESD protection in a circuit is provided. The method includes coupling a RC-delay element to an input of a plurality of serialized inverter elements, coupling an output of the plurality of serialized inverters with an ESD-triggered keeper device and a power clamp element, triggering the ESD-triggered keeper device to turn on during negative ESD events and conducting current by the power clamp element with assistance of the ESD-triggered keeper device to protect the circuit as a result of negative ESD events.
摘要翻译：一种静电放电（ESD）功率钳位电路，其包括耦合到多个串联反相器元件的RC延迟元件，其具有耦合到所述多个逆变器的功率钳位元件和ESD触发的保持器装置。在负模式ESD事件期间，ESD触发的保护装置被激活，并且帮助电源钳位元件上拉并强烈地传导电流以保护电路。另外，提供了电路中ESD保护的方法。该方法包括将RC延迟元件耦合到多个串联反相器元件的输入端，将多个串联反相器的输出与ESD触发的保持器装置和功率钳位元件耦合，将ESD触发的保持器装置触发在ESD ESD事件期间接通电源，并通过ESD触发的保护装置的辅助，通过电源钳位元件传导电流，以保护电路由于负ESD事件。

8. 发明申请

US20080308837A1 VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE SUCH AS A SILICON CONTROLLED RECTIFIER AND METHOD OF FORMING VERTICAL SOI CURRENT CONTROLLED DEVICES 有权
标题翻译：绝缘体（SOI）器件上的垂直电流控制硅如硅控制整流器及形成垂直SOI电流控制器件的方法
公开(公告)号：US20080308837A1
公开(公告)日：2008-12-18
申请号：US11762811
申请日：2007-06-14
申请人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher S. Putnam
发明人： Robert J. Gauthier, JR. , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher S. Putnam
IPC分类号： H01L29/74 , H01L21/20 , H01L21/332 , H01L21/84 , H01L29/00
CPC分类号： H01L27/0262
摘要： A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.
摘要翻译：具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片及其制造方法 s）。器件通过SOI表面层和绝缘体层形成在晶种孔中。通过衬底中的种子孔形成例如N型的掩埋扩散。掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。可以在掺杂的外延层上形成多晶硅，例如P型。与埋入扩散部的接触形成在接触衬里中。

9. 发明申请

US20080145993A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20080145993A1
公开(公告)日：2008-06-19
申请号：US12036319
申请日：2008-02-25
申请人： Robert J. Gauthier , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
发明人： Robert J. Gauthier , Junjun Li , Souvick Mitra , Mahmoud A. Mousa , Christopher Stephen Putnam
IPC分类号： H01L21/8228
CPC分类号： H01L29/7436 , H01L21/84 , H01L27/0262 , H01L27/1203
摘要： A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.
摘要翻译：硅控制整流器，制造硅控制整流器的方法和使用硅控制整流器作为集成电路的静电放电保护器件。硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为在平行于水平面的单个水平方向上。

10. 发明申请

US20080050880A1 STRUCTURE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE 审中-公开
标题翻译：具有可调触发电压的多器件半导体器件均匀触发的结构
公开(公告)号：US20080050880A1
公开(公告)日：2008-02-28
申请号：US11931634
申请日：2007-10-31
申请人： Michel Abou-Khalil , Robert Gauthier , Hongmei Li , Junjun Li , Souvick Mitra , Christopher Putnam
发明人： Michel Abou-Khalil , Robert Gauthier , Hongmei Li , Junjun Li , Souvick Mitra , Christopher Putnam
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/41733 , H01L29/41775 , H01L29/458 , H01L29/6653 , H01L29/7833 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.
摘要翻译：本发明提供了一种方法，其中提供了与扩展离子注入工艺无关的MOS沟道和硅化源极/漏极区之间的低电阻连接以及器件重叠电容。本发明的方法广泛地包括选择性地去除MOS结构的外部间隔物，然后在先前由外部间隔物保护的半导体衬底的暴露部分上选择性地镀覆金属或金属间化合物。本发明还提供了利用该方法形成的半导体结构。半导体结构包括硅化源/漏区和沟道区之间的低电阻连接，其包括选择性镀金属或金属间化合物。

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