专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07375585B2 Circuit and method for switching active loads of operational amplifier input stage 有权
标题翻译：用于切换运算放大器输入级有源负载的电路和方法
公开(公告)号：US07375585B2
公开(公告)日：2008-05-20
申请号：US11120088
申请日：2005-05-02
申请人： Dimitar T. Trifonov , Joy Y. Zhang
发明人： Dimitar T. Trifonov , Joy Y. Zhang
IPC分类号： H03F3/45
CPC分类号： H03F3/45219 , H03F2203/45424 , H03F2203/45504
摘要： An operational amplifier having a wide input common mode voltage range includes first (2) and second (3) differential input transistor pairs coupled to first (14) and second (15) tail current transistors. At least one of the first and second tail current transistor pairs is controlled by a common mode control circuit (4). A gate of the first tail current transistor (14) is coupled to the common mode control circuit (4) to turn the first tail current transistor on and to turn the second tail current transistor off when the common mode input voltage is below a common mode threshold voltage (CMTHR). A folded cascode stage (5) is driven by the first and second differential input transistor pairs. Switched active load transistors are coupled to active load transistors of the folded cascode stage and are operable in response to the common mode control circuit to divert part of a current produced by one of the first and second differential input pairs from the folded cascode circuit, depending on whether the common mode input voltage is above or below the common mode threshold voltage.
摘要翻译：具有宽输入共模电压范围的运算放大器包括耦合到第一（14）和第二（15）尾电流晶体管的第一（2）和第二（3）差分输入晶体管对。第一和第二尾电流晶体管对中的至少一个由共模控制电路（4）控制。当共模输入电压低于公共模式时，第一尾电流晶体管（14）的栅极耦合到共模控制电路（4），以使第一尾电流晶体管导通并使第二尾电流晶体管截止，阈值电压（CMTHR）。折叠的共源共栅级（5）由第一和第二差分输入晶体管对驱动。开关有源负载晶体管耦合到折叠共源共栅级的有源负载晶体管，并且响应于共模控制电路可操作以将部分由第一和第二差分输入对之一产生的电流从折叠共源共栅电路转移，这取决于关于共模输入电压是否高于或低于共模阈值电压。

2. 发明申请

US20120239841A1 SERIAL INTERFACE 有权
标题翻译：串行接口
公开(公告)号：US20120239841A1
公开(公告)日：2012-09-20
申请号：US13049694
申请日：2011-03-16
申请人： Dimitar T. Trifonov , Marco A. Gardner , Joe G. Di Bartolomeo
发明人： Dimitar T. Trifonov , Marco A. Gardner , Joe G. Di Bartolomeo
IPC分类号： G06F13/14
CPC分类号： G06F13/4282
摘要： A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.
摘要翻译：提供了一种方法。通过单线总线的IC的输入引脚接收通信，其中通信包括命令字节。如果命令字节是初始化命令字节，则执行自寻址操作以识别IC的总线地址。或者，如果命令字节是数据移动命令字节，则执行数据移动操作。当执行数据移动操作时，如果来自命令字节的操作地址与总线地址匹配，则IC的总线接口从透明模式设置为操作模式，使得可以访问在命令字节中识别的寄存器和数据移动可以执行寄存器。

3. 发明授权

US07595676B2 Comparator and method with controllable threshold and hysteresis 有权
公开(公告)号：US07595676B2
公开(公告)日：2009-09-29
申请号：US11880582
申请日：2007-07-23
申请人： Dimitar T. Trifonov
发明人： Dimitar T. Trifonov
IPC分类号： H03K3/00
CPC分类号： H03K5/2481 , H03K3/3565 , H03K5/088
摘要： A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin−), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref−) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load. An output stage (6A) produces a comparator output voltage (Vout) in response to an output (V2) produced by the first and second (11) differential input stages. A switching threshold of the comparator is determined by a difference between the first and second reference voltages.

4. 发明申请

US20100019842A1 Low-noise, wide offset range, programmable input offset amplifier front end and method 有权
标题翻译：低噪声，宽偏移范围，可编程输入失调放大器前端和方法
公开(公告)号：US20100019842A1
公开(公告)日：2010-01-28
申请号：US12229278
申请日：2008-08-21
申请人： Tony R. Larson , Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Tony R. Larson , Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： H03F1/02 , H03G3/00
CPC分类号： H03F3/45475 , H03F3/45183 , H03F3/45197 , H03F3/45928 , H03F3/72 , H03F2203/45101 , H03F2203/45482 , H03F2203/45494 , H03F2203/45616 , H03F2203/45678 , H03F2203/45681
摘要： A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin−) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (−) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.
摘要翻译：可编程偏移放大器包括具有与第一（Vin +）和第二（Vin-）输入电压耦合的差分连接的源极和第一（M1）和第二（M2）输入晶体管。尾电流（Itail1）在第一和第二输入晶体管之间共享。第一（M3）和第二（M4）负载装置分别耦合在参考电压和第一和第二输入晶体管的漏极之间。输出级（13）具有耦合到第二输入晶体管的漏极的第一输入（+）和耦合到第一输入晶体管的漏极的第二输入（ - ）。可编程电压变化在可编程输入偏移电路的输入元件上产生，以引起与输入晶体管的电极相关联的偏移电压的变化，其被反射回到放大器输入端以提供大的可编程输入参考偏移电压。

5. 发明申请

US20090073011A1 CIRCUIT AND METHOD FOR GAIN ERROR CORRECTION IN ADC 有权
标题翻译： ADC中增益误差校正的电路和方法
公开(公告)号：US20090073011A1
公开(公告)日：2009-03-19
申请号：US11901355
申请日：2007-09-17
申请人： Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： H03M1/06
CPC分类号： H03M1/1019 , H03M1/40 , H03M1/46 , H03M3/382 , H03M3/43 , H03M3/456
摘要： Gain errors are corrected in an ADC chip including an integrator (17), a comparator (30), and a digital filter (37) by storing a gain-adjusted LSB size based on measured gain error in a memory (44). The gain-adjusted LSB size is applied to the digital filter to cause gain-adjusted LSB size values to be added to or subtracted from accumulated content of the digital filter in accordance with a first or second state, respectively, of the comparator (30) during each cycle of the ADC. The final accumulated content after all required cycles of the ADC is a gain-corrected digital output signal (Dout(gain-corrected)).
摘要翻译：通过将经增益调整的LSB大小基于测量的增益误差存储在存储器（44）中，在包括积分器（17），比较器（30）和数字滤波器（37）的ADC芯片中校正增益误差。经增益调整的LSB大小被施加到数字滤波器，以使得根据比较器（30）的第一或第二状态，增加经调整的LSB大小值被添加到数字滤波器的累加内容或从累积内容中减去，在ADC的每个周期。 ADC所需的所有周期之后的最终累加内容是增益校正的数字输出信号（Dout（增益校正））。

6. 发明授权

US07504977B2 Hybrid delta-sigma/SAR analog to digital converter and methods for using such 有权
标题翻译：混合Δ-Σ/ SAR模数转换器及其使用方法
公开(公告)号：US07504977B2
公开(公告)日：2009-03-17
申请号：US11738566
申请日：2007-04-23
申请人： Jerry L. Doorenbos , Marco A. Gardner , Dimitar T. Trifonov
发明人： Jerry L. Doorenbos , Marco A. Gardner , Dimitar T. Trifonov
IPC分类号： H03M3/00
CPC分类号： H03M1/145 , H03M1/46 , H03M3/43 , H03M3/456 , H03M3/46
摘要： Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.
摘要翻译：公开了用于捕获数据的各种系统和方法。例如，本发明的一些实施例提供了使用基于Δ-Σ的模数转换器执行第一模数转换的方法，以及使用基于SAR的模数转换器执行第二模数转换。 Δ-Σ转换器提供转换结果的第一部分，并且基于SAR的模数转换器提供转换结果的第二部分。所述方法还包括将转换结果的第一部分与转换结果的第二部分组合以产生组合转换结果。

7. 发明申请

US20090027086A1 Comparator and method with controllable threshold and hysteresis 有权
标题翻译：具有可控阈值和滞后的比较器和方法
公开(公告)号：US20090027086A1
公开(公告)日：2009-01-29
申请号：US11880582
申请日：2007-07-23
申请人： Dimitar T. Trifonov
发明人： Dimitar T. Trifonov
IPC分类号： H03K5/22
CPC分类号： H03K5/2481 , H03K3/3565 , H03K5/088
摘要： A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin−), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref−) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load. An output stage (6A) produces a comparator output voltage (Vout) in response to an output (V2) produced by the first and second (11) differential input stages. A switching threshold of the comparator is determined by a difference between the first and second reference voltages.
摘要翻译：比较器（12A，12B）包括第一差分输入级（10），包括第一（MN2）和第二输入晶体管（MN3）和负载（MP9，MP10），第一输入晶体管（MN2）和分别耦合到第一输入电压（Vin-），第一尾电流源和负载的漏极。第二输入晶体管具有耦合到第二输入电压（Vin +）和第一尾电流源的栅极和源极。第二差分输入级（11）包括第三（MN4）和第四（MN5）输入晶体管，第三输入晶体管分别具有耦合到第一参考电压（Vref +）和第二尾电流源的栅极和源极。第四输入晶体管（MN5）分别具有耦合到第二参考电压（Vref-）和第二尾电流源的栅极和源极。第三和第四输入晶体管的漏极耦合到负载。输出级（6A）响应于由第一和第二（11）差分输入级产生的输出（V2）产生比较器输出电压（Vout）。比较器的切换阈值由第一和第二参考电压之间的差确定。

8. 发明申请

US20080100489A1 Digital to analog converter architecture and method having low switch count and small output impedance 有权
标题翻译：具有低开关数和小输出阻抗的数模转换器结构和方法
公开(公告)号：US20080100489A1
公开(公告)日：2008-05-01
申请号：US11880568
申请日：2007-07-23
申请人： Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： H03M1/66
CPC分类号： H03M1/682 , H03M1/765 , H03M1/785
摘要： A digital to analog converter includes a coarse resolution resistor circuit (11) coupled between a first voltage (Vin) and an intermediate voltage (V0) to produce coarse resolution node voltages (V0, . . . V240), and also includes a fine resolution resistor circuit (20) coupled between the intermediate voltage and a second voltage (GND). One of the coarse resolution node voltages is selected in response to a group of MSB bits of a digital input (D0,1 . . . ) to produce a first output voltage (Vout2), and one of the fine resolution node voltages is selected in response to group of LSB bits of the digital input to produce a second output voltage (Vout1), the second output voltage (Vout1) and the first output voltage (Vout2) providing a differential analog output signal (Vout1−Vout2). In one embodiment, the coarse resolution and fine resolution resistor circuits are string resistor circuits, and in another embodiment they are modified R-2R networks.
摘要翻译：数模转换器包括耦合在第一电压（Vin）和中间电压（V 0）之间的粗分辨率电阻电路（11），以产生粗分辨率节点电压（V 0，...，V 240），并且还包括耦合在中间电压和第二电压（GND）之间的精细分辨率电阻电路（20）。响应于数字输入（D 0,1 ...）的一组MSB位选择粗分辨率节点电压之一以产生第一输出电压（Vout 2），并且精细分辨率节点电压之一为响应于数字输入的一组LSB位而选择以产生第二输出电压（Vout 1），第二输出电压（Vout 1）和第一输出电压（Vout 2）提供差分模拟输出信号（Vout 1 - Vout 2）。在一个实施例中，粗分辨率和精细分辨率电阻电路是串电阻电路，在另一实施例中，它们是修改的R-2R网络。

9. 发明申请

US20130257507A1 Analog Multiplier and Method for Current Shunt Power Measurements 有权
标题翻译：用于电流分流功率测量的模拟乘法器和方法
公开(公告)号：US20130257507A1
公开(公告)日：2013-10-03
申请号：US13438333
申请日：2012-04-03
申请人： Tony R. Larson , Srikanth Vellore Avadhanam Ramamurthy , Dimitar T. Trifonov
发明人： Tony R. Larson , Srikanth Vellore Avadhanam Ramamurthy , Dimitar T. Trifonov
IPC分类号： G06G7/16
CPC分类号： G06G7/164
摘要： Multiplier circuitry includes first multiplier circuit including a first transistor having an emitter coupled to a first conductor, a base coupled to a second conductor, and a collector coupled to a third conductor, a second transistor having an emitter coupled to the first conductor, a base coupled to a fourth conductor, and a collector coupled to a fifth conductor, a third transistor having an emitter coupled to the second conductor and a base and collector coupled to a supply voltage, and a fourth transistor having an emitter coupled to the fourth conductor and a base and collector coupled to the supply voltage. Chopper includes a first switch to provide a chopped differential signal between the second and fourth conductors and a second switch for un-chopping a first differential output signal produced between the third and fifth conductors to provide an un-chopped differential output signal between the third and fifth conductors.
摘要翻译：乘法器电路包括第一乘法器电路，其包括第一晶体管，其具有耦合到第一导体的发射极，耦合到第二导体的基极和耦合到第三导体的集电极，具有耦合到第一导体的发射极的第二晶体管，耦合到第四导体和耦合到第五导体的集电极，具有耦合到第二导体的发射极和耦合到电源电压的基极和集电极的第三晶体管，以及耦合到第四导体的发射极的第四晶体管，耦合到电源电压的基极和集电极。斩波器包括：第一开关，用于在第二和第四导体之间提供斩波的差分信号;以及第二开关，用于对在第三和第五导体之间产生的第一差分输出信号进行斩波，以在第三和第四导体之间提供未切碎的差分输出信号，第五导体。

10. 发明授权

US08324881B2 Bandgap reference circuit with sampling and averaging circuitry 有权
标题翻译：带采样和平均电路的带隙参考电路
公开(公告)号：US08324881B2
公开(公告)日：2012-12-04
申请号：US12799288
申请日：2010-04-21
申请人： Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： G05F3/30
CPC分类号： G05F3/30 , H03F1/303 , H03F2200/447
摘要： A circuit for generating a band gap reference voltage (VREF) includes circuitry (I3×7) for supplying a first current to a first conductor (NODE1) and a second current to a second conductor (NODE2). The first conductor is successively coupled to a plurality of diodes (Q0×16), respectively, in response to a digital signal (CTL-VBE) to cause the first current to successively flow into selected diodes. The second conductor is coupled to collectors of the diodes which are not presently coupled to the first conductor. The diodes are successively coupled to the first conductor so that the first current causes the diodes, respectively, to produce relatively large VBE voltages on the first conductor and the second current causes sets of the diodes not coupled to the first conductor to produce relatively small VBE voltages on the second conductor. The relatively large and small VBE voltages provide differential band gap charges (QCA-QCB) which are averaged to provide a stable band gap reference voltage (VREF).
摘要翻译：用于产生带隙参考电压（VREF）的电路包括用于向第一导体（NODE1）提供第一电流的电路（I3×7）和向第二导体（NODE2）提供第二电流的电路。第一导体响应于数字信号（CTL-VBE）分别依次耦合到多个二极管（Q0×16），以使第一电流连续地流入选定的二极管。第二导体耦合到当前不耦合到第一导体的二极管的集电极。二极管连续地耦合到第一导体，使得第一电流分别导致二极管在第一导体上产生相对较大的VBE电压，并且第二电流使得未耦合到第一导体的二极管组产生相对较小的VBE 第二导体上的电压。相对较大和较小的VBE电压提供差分带隙电荷（QCA-QCB），其被平均以提供稳定的带隙参考电压（VREF）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式