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1. 发明申请

US20070247206A1 Programmable trigger delays 审中-公开
标题翻译：可编程触发延迟
公开(公告)号：US20070247206A1
公开(公告)日：2007-10-25
申请号：US11408400
申请日：2006-04-21
申请人： Dietrich Vook , Stanley Jefferson , Vamsi Srikantam
发明人： Dietrich Vook , Stanley Jefferson , Vamsi Srikantam
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/13 , H03K5/135 , H03K2005/00026 , H03K2005/00058
摘要： Aspects of the disclosure embody methods and circuits for delaying a trigger signal. In one embodiment, a trigger delay circuit receives a trigger-in signal, delays some predetermined and programmable time delay and then outputs a trigger-out signal. The trigger delay circuit, in one embodiment, includes a programmable trigger circuit that time stamps the input trigger signal, delay for a predetermined time, and output the output trigger signal after the predetermined time.
摘要翻译：本公开的方面体现了用于延迟触发信号的方法和电路。在一个实施例中，触发延迟电路接收触发输入信号，延迟一些预定和可编程的时间延迟，然后输出触发输出信号。触发延迟电路在一个实施例中包括可编程触发电路，其对输入触发信号进行时间戳，延迟预定时间，并在预定时间之后输出输出触发信号。

2. 发明申请

US20070127318A1 Time stamping events for fractions of a clock cycle 有权
$Time stamping events for fractions of a clock cycle$
标题翻译：时间周期的时间戳冲突事件
公开(公告)号：US20070127318A1
公开(公告)日：2007-06-07
申请号：US11292472
申请日：2005-12-02
申请人： Vamsi Srikantam , Andrew Fernandez , Dietrich Vook
发明人： Vamsi Srikantam , Andrew Fernandez , Dietrich Vook
IPC分类号： G04F8/00
CPC分类号： H04L7/0338
摘要： Generally, the embodiments are directed to circuits and methods for time stamping an event at a fraction of a clock cycle. A time stamping circuit comprises two or more detection circuits. The detection circuits receive an event-in signal and generate event signals based on a clock phase at which the event-in signal was received. A decoder receives the event signals and outputs an event-out signal and a time stamp that represents the phase at which the event-in signal was detected. By time stamping the event-in signal to a phase division, the time stamping circuit detects event signals that occur at a rate faster than the clock cycle.
摘要翻译：通常，实施例涉及用于以几分之一时钟周期对事件进行时间戳的电路和方法。时间戳电路包括两个或更多个检测电路。检测电路接收事件输入信号，并且基于接收到事件输入信号的时钟相位产生事件信号。解码器接收事件信号并输出表示检测到事件输入信号的相位的事件输出信号和时间戳。通过将事件进入时间戳入相位分段，时间戳电路以比时钟周期更快的速率检测出发生的事件信号。

3. 发明申请

US20070126488A1 Triggering events at fractions of a clock cycle 失效
$Triggering events at fractions of a clock cycle$
标题翻译：以时钟周期的分数触发事件
公开(公告)号：US20070126488A1
公开(公告)日：2007-06-07
申请号：US11292477
申请日：2005-12-02
申请人： Dietrich Vook , Vamsi Srikantam , Andrew Fernandez
发明人： Dietrich Vook , Vamsi Srikantam , Andrew Fernandez
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03K5/135 , H03K2005/00058 , H03K2005/00241
摘要： Generally, the embodiments presented are directed to circuits and methods for triggering an event at a fraction of a clock cycle. A triggering circuit can comprise two or more input circuits that output an event signal. The event signal is received by one of two or more delay circuits that trigger the event signal at a predetermined phase of the clock cycle by moving the event signal from a first clock domain to another clock domain. By triggering the event at a phase division, the triggering circuit outputs signals at a rate faster than the clock cycle.
摘要翻译：通常，所呈现的实施例涉及用于以一小时时钟周期触发事件的电路和方法。触发电路可以包括输出事件信号的两个或多个输入电路。通过将事件信号从第一时钟域移动到另一个时钟域，由两个或更多个延迟电路之一接收事件信号，该延迟电路在时钟周期的预定相位触发事件信号。通过在相位分割触发事件，触发电路以比时钟周期更快的速率输出信号。

4. 发明授权

US06275083B1 Low operational power, low leakage power D-type flip-flop 失效
标题翻译：低功耗，低漏电功率D型触发器
公开(公告)号：US06275083B1
公开(公告)日：2001-08-14
申请号：US09655206
申请日：2000-09-05
申请人： Mario Martinez , Vamsi Srikantam
发明人： Mario Martinez , Vamsi Srikantam
IPC分类号： H03K312
CPC分类号： H03K19/0016
摘要： A flip-flop having a sleep mode in which power consumption is reduced. The flip-flop comprises a clock input, a data input, an input stage, an input gate, an output stage and an output clamp. The input gate is interposed between the data input and the input stage and operates in the sleep mode to isolate the input stage from the data input. The output stage is coupled to the input stage and includes an output having a first output state and a second output state. The output clamp operates in the sleep mode to set the output stage to a predetermined state regardless of the data states at the data input and the clock input. The predetermined state is the one of the output states in which the leakage power consumption of the flip-flop is less than in the other of the output states. The predetermined state may alternatively be the one of the output states in which the leakage power consumption of circuitry connected to the output of the flip-flop is less than in the other of the output states. As a further alternative, the predetermined state may be the one of the output states in which the leakage power consumption of a digital electronic circuit of which the flip-flop forms part is less than in the other of the output states.
摘要翻译：具有睡眠模式的触发器，其中功耗降低。触发器包括时钟输入，数据输入，输入级，输入门，输出级和输出钳位。输入门介于数据输入和输入级之间，并在睡眠模式下工作，以将输入级与数据输入隔离开。输出级耦合到输入级并且包括具有第一输出状态和第二输出状态的输出。无论数据输入和时钟输入的数据状态如何，输出钳位电路在睡眠模式下工作，将输出级设置为预定状态。预定状态是其中触发器的泄漏功耗小于另一个输出状态的输出状态之一。预定状态可以替代地是连接到触发器的输出的电路的泄漏功耗小于另一个输出状态的输出状态之一。作为另一替代方案，预定状态可以是其中触发器形成的数字电子电路的泄漏功耗小于另一个输出状态的输出状态之一。

5. 发明申请

US20070024904A1 Imaging serial interface ROM 审中-公开
标题翻译：成像串行接口ROM
公开(公告)号：US20070024904A1
公开(公告)日：2007-02-01
申请号：US11192827
申请日：2005-07-28
申请人： Richard Baer , Vamsi Srikantam
发明人： Richard Baer , Vamsi Srikantam
IPC分类号： G06K15/00
CPC分类号： H04N5/335
摘要： Imaging serial interface ROM (ISIROM). An integrated circuit imaging device presents to external circuitry as a read-only memory (ROM) with a serial interface. The ISIROM contains internal memory which stores data from the imaging array. When active, the imaging array automatically fills an image buffer in the internal memory with image data. This image data may be accessed by external circuitry in random-access fashion. Control and status registers may be used to start and stop the imaging process, set and interrogate imaging parameters. The ISIROM may also include auxiliary processing circuitry to perform functions such as image compression, scaling, edge and feature extraction, and the like.
摘要翻译：成像串行接口ROM（ISIROM）。集成电路成像装置将外部电路呈现为具有串行接口的只读存储器（ROM）。 ISIROM包含存储来自成像阵列的数据的内部存储器。激活时，成像阵列会自动使用图像数据填充内部存储器中的图像缓冲区。该图像数据可以由外部电路以随机访问方式访问。控制和状态寄存器可用于启动和停止成像过程，设置和询问成像参数。 ISIROM还可以包括执行诸如图像压缩，缩放，边缘和特征提取等功能的辅助处理电路。

6. 发明申请

US20070024713A1 Imaging parallel interface RAM 审中-公开
标题翻译：成像并行接口RAM
公开(公告)号：US20070024713A1
公开(公告)日：2007-02-01
申请号：US11192894
申请日：2005-07-28
申请人： Richard Baer , Vamsi Srikantam
发明人： Richard Baer , Vamsi Srikantam
IPC分类号： H04N5/225
CPC分类号： H04N5/335
摘要： Imaging Parallel Interface Random Access Memory (IPIRAM). An integrated circuit imaging device presents to external circuitry as a static, parallel-interface RAM. Internally, a two-port RAM has access resolved by contention logic to permit access by external circuitry or internal imaging. The RAM is organized as one or more image buffers and a set of memory-mapped control and status registers. The imaging array, when active, automatically fills an image buffer with image data, which may be accessed by external circuitry in random-access fashion. Control and status registers may be used to start and stop the imaging process, set and interrogate imaging parameters. The IPIRAM may also include auxiliary processing circuitry to perform functions such as image compression, scaling, edge and feature extraction, and the like.
摘要翻译：成像并行接口随机存取存储器（IPIRAM）。集成电路成像装置将外部电路呈现为静态的并行接口RAM。在内部，双端口RAM通过争用逻辑解决访问，以允许外部电路或内部成像进行访问。 RAM被组织为一个或多个图像缓冲器和一组存储器映射的控制和状态寄存器。成像阵列处于活动状态时，会以图像数据自动填充图像缓冲区，图像数据可以通过外部电路以随机访问方式访问。控制和状态寄存器可用于启动和停止成像过程，设置和询问成像参数。 IPIRAM还可以包括执行诸如图像压缩，缩放，边缘和特征提取等功能的辅助处理电路。

7. 发明申请

US20060250288A1 SYSTEM AND METHOD FOR TIMING CALIBRATION OF TIME-INTERLEAVED DATA CONVERTERS 有权
标题翻译：用于定时校正时间间隔数据转换器的系统和方法
公开(公告)号：US20060250288A1
公开(公告)日：2006-11-09
申请号：US11120698
申请日：2005-05-03
申请人： Andrew Fernandez , Vamsi Srikantam , Robert Neff , Kenneth Poulton
发明人： Andrew Fernandez , Vamsi Srikantam , Robert Neff , Kenneth Poulton
IPC分类号： H03M1/10
CPC分类号： H03M1/10 , H03M1/1205 , H03M1/662
摘要： A method for calibrating time interleaved samplers comprising applying a calibration signal to a time-interleaved sampling device, wherein the signal is coherent with at least one sample clock on the device and is periodic and has a predetermined spectral content and frequency, sampling, by said time-interleaved sampling device, the calibration signal at a plurality of phases to form samples, averaging the formed samples, and calculating the phase error of each sample based on the average calibration signal sample.
摘要翻译：一种用于校准时间交织采样器的方法，包括将校准信号施加到时间交织的采样设备，其中所述信号与所述设备上的至少一个采样时钟相干，并且是周期性的并且具有预定的频谱含量和频率，由所述时间交织采样装置，多个相位的校准信号，以形成样本，对所形成的样本进行平均，以及基于平均校准信号样本计算每个样本的相位误差。

8. 发明申请

US20050213683A1 Digital modulator employing a polyphase up-converter structure 有权
标题翻译：采用多相上变频器结构的数字调制器
公开(公告)号：US20050213683A1
公开(公告)日：2005-09-29
申请号：US10814472
申请日：2004-03-29
申请人： Paul Corredoura , Vamsi Srikantam
发明人： Paul Corredoura , Vamsi Srikantam
IPC分类号： H03D7/00 , H03C3/00 , H03C3/40 , H04L27/20 , H04L27/04
CPC分类号： H03C3/40
摘要： An upconverting circuit is disclosed. The upconverting circuit includes a polyphase component generator that provides Np polyphase components at each input polyphase cycle, wherein Np>2 on each input polyphase cycle defined by a clock. A memory stores the polyphase components from at least one polyphase cycle prior to the current polyphase cycle. A plurality of filters process the polyphase components stored in the memory. Each filter processes a plurality of the polyphase components to generate a filtered polyphase component corresponding to that filter. A multiplexer outputs the filtered polyphase components in a predetermined order to generate a filtered output signal. In one embodiment, each filter utilizes the same functional relationship to generate the filtered polyphase components. In another embodiment, the memory is a shift register. The filters can be of arbitrary complexity.
摘要翻译：公开了一种上变频电路。上变频电路包括多相分量发生器，其在每个输入多相周期处提供N p个多相分量，其中在由时钟限定的每个输入多相周期上的N p P 2。存储器存储来自当前多相循环之前的至少一个多相循环的多相成分。多个滤波器处理存储在存储器中的多相分量。每个滤波器处理多个多相分量以产生对应于该滤波器的滤波多相分量。多路复用器以预定顺序输出滤波后的多相分量以产生经滤波的输出信号。在一个实施例中，每个滤波器利用相同的功能关系来产生滤波的多相分量。在另一个实施例中，存储器是移位寄存器。过滤器可以是任意复杂的。

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