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1. 发明授权

US07482243B2 Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique 失效
标题翻译：超薄Si沟道MOSFET采用自对准氧注入和镶嵌技术
公开(公告)号：US07482243B2
公开(公告)日：2009-01-27
申请号：US11436756
申请日：2006-05-18
申请人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
发明人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
IPC分类号： H01L21/76 , H01L21/338 , H01L21/84 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78609 , H01L29/78684
摘要： The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.
摘要翻译：本发明提供一种形成具有低外部电阻的薄沟道MOSFET的方法。该方法包括在基板的顶部形成伪栅极区域; 通过所述伪栅极注入形成氧化物的掺杂剂，以在与沟道区域的伪栅极区对准的衬底的一部分中产生局部氧化物区域; 形成邻接所述沟道区的源/漏扩展区; 并用栅极导体代替虚拟栅极。

2. 发明授权

US07075150B2 Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique 有权
公开(公告)号：US07075150B2
公开(公告)日：2006-07-11
申请号：US10725849
申请日：2003-12-02
申请人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
发明人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
IPC分类号： H01L27/01
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772 , H01L29/78609 , H01L29/78684
摘要： The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

3. 发明授权

US07247569B2 Ultra-thin Si MOSFET device structure and method of manufacture 失效
标题翻译：超薄Si MOSFET器件结构及制造方法
公开(公告)号：US07247569B2
公开(公告)日：2007-07-24
申请号：US10725848
申请日：2003-12-02
申请人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
发明人： Diane C. Boyd , Bruce B. Doris , Meikei Ieong , Devendra K. Sadana
IPC分类号： H01L21/302
CPC分类号： H01L21/28194 , H01L21/26533 , H01L21/28202 , H01L29/1083 , H01L29/49 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/78
摘要： The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.
摘要翻译：本发明包括用于形成超薄沟道MOSFET的方法和由其制造的超薄沟道MOSFET。具体地说，该方法包括：在SOI层的下方提供具有掩埋绝缘层的SOI衬底; 在SOI层顶上形成焊盘堆叠; 通过所述垫堆叠的顶部形成具有通道的块掩模; 在所述掩埋绝缘层的顶部上的所述SOI层中提供局部氧化物区域，从而使所述SOI层的一部分变薄，所述局部氧化物区域与所述沟道通孔自对准; 在通道通道中形成一个门; 至少去除阻挡掩模; 以及在与SOI层的薄化部分邻接的SOI层中形成源极/漏极延伸部。提供局部氧化物区域还包括通过沟道通孔将氧掺杂剂注入到SOI层的一部分中; 并退火掺杂剂以产生局部氧化物区域。

4. 发明授权

US06911383B2 Hybrid planar and finFET CMOS devices 失效
标题翻译：混合平面和finFET CMOS器件
公开(公告)号：US06911383B2
公开(公告)日：2005-06-28
申请号：US10604097
申请日：2003-06-26
申请人： Bruce B. Doris , Diane C. Boyd , Meikei Ieong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
发明人： Bruce B. Doris , Diane C. Boyd , Meikei Ieong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/49 , H01L29/786 , H01L21/3205
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.
摘要翻译：本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上，绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。还提供了一种形成集成电路的方法。在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

5. 发明授权

US07759772B2 Method to form Si-containing SOI and underlying substrate with different orientations 失效
标题翻译：形成含Si的SOI和具有不同取向的下层衬底的方法
公开(公告)号：US07759772B2
公开(公告)日：2010-07-20
申请号：US11550681
申请日：2006-10-18
申请人： Meikei Ieong , Devendra K. Sadana , Ghavam Shahidi
发明人： Meikei Ieong , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L21/76251 , H01L21/2007
摘要： A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.
摘要翻译：一种形成包含上层含Si层和下层含Si层的混合SOI衬底的方法，其中上层含Si层和下层含Si层具有不同的结晶取向。根据本发明，掩埋绝缘区域可以位于一个含硅层内或通过位于两个含Si层之间的界面。

6. 发明申请

US20080254594A1 STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS 失效
标题翻译：应变硅CMOS混合晶体取向
公开(公告)号：US20080254594A1
公开(公告)日：2008-10-16
申请号：US12143912
申请日：2008-06-23
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/30
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

7. 发明申请

US20080128866A1 METHOD TO FORM Si-CONTAINING SOI AND UNDERLYING SUBSTRATE WITH DIFFERENT ORIENTATIONS 失效
标题翻译：形成含Si的方法和基底不同方向的方法
公开(公告)号：US20080128866A1
公开(公告)日：2008-06-05
申请号：US11550681
申请日：2006-10-18
申请人： Meikei Ieong , Devendra K. Sadana , Ghavam Shahidi
发明人： Meikei Ieong , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L21/76251 , H01L21/2007
摘要： A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.
摘要翻译：一种形成包含上层含Si层和下层含Si层的混合SOI衬底的方法，其中上层含Si层和下层含Si层具有不同的结晶取向。根据本发明，掩埋绝缘区域可以位于一个含硅层内或通过位于两个含Si层之间的界面。

8. 发明授权

US07141457B2 Method to form Si-containing SOI and underlying substrate with different orientations 失效
公开(公告)号：US07141457B2
公开(公告)日：2006-11-28
申请号：US10992150
申请日：2004-11-18
申请人： Meikei Ieong , Devendra K. Sadana , Ghavam Shahidi
发明人： Meikei Ieong , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L21/76251 , H01L21/2007
摘要： A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.

9. 发明授权

US07691688B2 Strained silicon CMOS on hybrid crystal orientations 失效
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US07691688B2
公开(公告)日：2010-04-06
申请号：US12143912
申请日：2008-06-23
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

10. 发明授权

US07402466B2 Strained silicon CMOS on hybrid crystal orientations 有权
标题翻译：应变硅CMOS在混合晶体取向上
公开(公告)号：US07402466B2
公开(公告)日：2008-07-22
申请号：US11492271
申请日：2006-07-25
申请人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
发明人： Kevin K. Chan , Meikei Ieong , Alexander Reznicek , Devendra K. Sadana , Leathen Shi , Min Yang
IPC分类号： H01L21/00
CPC分类号： H01L29/7842 , H01L21/2022 , H01L21/76275 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78687
摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.
摘要翻译：提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。该方法提供混合基板，其中至少一个器件层包括应变Si。

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