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1. 发明申请

US20080181012A1 Memory Device with Adaptive Sense Unit and Method of Reading a Cell Array 有权
标题翻译：具有自适应感知单元的存储器件和读取单元阵列的方法
公开(公告)号：US20080181012A1
公开(公告)日：2008-07-31
申请号：US11668753
申请日：2007-01-30
申请人： Detlev Richter , Mirko Reissmann , Volker Zipprich-Rasch , Gert Kobernik , Uwe Augustin , Konrad Seidel , Andreas Kux , Hans Heitzer , Daniel-Andre Lohr , Soren Irmer
发明人： Detlev Richter , Mirko Reissmann , Volker Zipprich-Rasch , Gert Kobernik , Uwe Augustin , Konrad Seidel , Andreas Kux , Hans Heitzer , Daniel-Andre Lohr , Soren Irmer
IPC分类号： G11C16/26
CPC分类号： G11C16/10 , G11C16/26
摘要： A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.
摘要翻译：提供了一种存储器件，其包括能够在至少两个状态之间切换的存储器单元，其中用于检测当前状态的检测信号的阈值取决于存储器单元的数据内容。平行于用户数据块，包括第一状态的预定位数的主控制字被存储在单元阵列的检查部分中。通过应用不同幅度的感测信号来读取检查部分，其中在每种情况下获得辅助控制字。通过检查每个辅助控制字中的第一状态的位数，可以检查当前感测信号向感应窗口极限的幅度的边缘，并且感测信号幅度可以永久地适应于感测窗漂移，从而增强存储设备的可靠性。

2. 发明授权

US07489563B2 Memory device with adaptive sense unit and method of reading a cell array 有权
标题翻译：具有自适应感测单元的存储器件和读取单元阵列的方法
公开(公告)号：US07489563B2
公开(公告)日：2009-02-10
申请号：US11668753
申请日：2007-01-30
申请人： Detlev Richter , Mirko Reissmann , Volker Zipprich-Rasch , Gert Köbernik , Uwe Augustin , Konrad Seidel , Andreas Kux , Hans Heitzer , Daniel-André Löhr , Sören Irmer
发明人： Detlev Richter , Mirko Reissmann , Volker Zipprich-Rasch , Gert Köbernik , Uwe Augustin , Konrad Seidel , Andreas Kux , Hans Heitzer , Daniel-André Löhr , Sören Irmer
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C16/26
摘要： A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.
摘要翻译：提供了一种存储器件，其包括能够在至少两个状态之间切换的存储器单元，其中用于检测当前状态的检测信号的阈值取决于存储器单元的数据内容。平行于用户数据块，包括第一状态的预定位数的主控制字被存储在单元阵列的检查部分中。通过应用不同幅度的感测信号来读取检查部分，其中在每种情况下获得辅助控制字。通过检查每个辅助控制字中的第一状态的位数，可以检查当前感测信号向感应窗口极限的幅度的边缘，并且感测信号幅度可以永久地适应于感测窗漂移，从而增强存储设备的可靠性。

3. 发明申请

US20080049512A1 Nonvolatile memory device and method of programming the same 审中-公开
标题翻译：非易失存储器件及其编程方法
公开(公告)号：US20080049512A1
公开(公告)日：2008-02-28
申请号：US11508336
申请日：2006-08-23
申请人： Konrad Seidel , Uwe Augustin , Gert Koebernick , Soren Irmer , Daniel-Andre Loehr , Volker Zipprich-Rasch , Mirko Reissmann
发明人： Konrad Seidel , Uwe Augustin , Gert Koebernick , Soren Irmer , Daniel-Andre Loehr , Volker Zipprich-Rasch , Mirko Reissmann
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C16/10 , G11C16/349
摘要： A method for conducting programming and erasure of charge-trapped memory devices includes: conducting at least one program/erase cycle of a charge-trapped memory device on the basis of a given threshold voltage of the charge-trapped memory device as a reference point; determining a wear-level of the erasing procedure; shifting the reference point according to a result of the determination of the wear-level; conducting one or more program/erase cycle on the basis of the shifted threshold; and conducting read and verify operations on the basis of the shifted threshold.
摘要翻译：用于执行电荷捕获存储器件的编程和擦除的方法包括：基于电荷捕获的存储器件的给定阈值电压作为参考点进行电荷俘获存储器件的至少一个编程/擦除周期; 确定擦除程序的磨损水平; 根据磨损水平的确定结果移动参考点; 基于偏移的阈值进行一个或多个编程/擦除周期; 并基于偏移的阈值进行读取和验证操作。

4. 发明申请

US20080013390A1 Memory array architecture and method for high-speed distribution measurements 有权
标题翻译：用于高速分布测量的存储器阵列架构和方法
公开(公告)号：US20080013390A1
公开(公告)日：2008-01-17
申请号：US11485185
申请日：2006-07-12
申请人： Volker Zipprich-Rasch
发明人： Volker Zipprich-Rasch
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/44 , G11C29/50 , G11C29/50004
摘要： A method includes an initial process of selecting a memory cell within the memory array and an operating condition under which the memory cell is to be tested. The memory cell is tested under the specified operating condition, and a measured response obtained therefrom. Based upon the measured response, a determination is made as to whether the memory cell passes or fails a predetermined criterion. The pass/fail result is communicated to a counter that is integrated on-chip with the memory array, the counter operable to accumulate a total number of pass or fail results supplied thereto. The aforementioned processes are repeated for at least one different memory cell, whereby the new memory cell is tested under the aforementioned operating conditions. Subsequently, a data value representing the accumulated number of pass or fail results is output from the on-chip counter.
摘要翻译：一种方法包括选择存储器阵列内的存储器单元的初始过程和要测试存储器单元的操作条件。在指定的操作条件下测试存储单元，并从其获得测量的响应。基于测量的响应，确定存储器单元是否通过或失败了预定标准。通过/失败结果被传送到与存储器阵列集成在一起的计数器，计数器可操作以累加提供给它的总数或失败结果的总数。对于至少一个不同的存储器单元重复上述处理，由此在上述操作条件下测试新的存储单元。随后，从片上计数器输出表示通过或失败结果的累积数的数据值。

5. 发明申请

US20080195903A1 NON-VOLATILE MEMORY DEVICE WITH BUILT-IN TEST CONTROL UNIT AND METHODS OF TESTING AND REPAIRING A CELL ARRAY 审中-公开
标题翻译：具有内置测试控制单元的非易失性存储器件和测试和修复单元阵列的方法
公开(公告)号：US20080195903A1
公开(公告)日：2008-08-14
申请号：US11674853
申请日：2007-02-14
申请人： Volker Zipprich-Rasch
发明人： Volker Zipprich-Rasch
IPC分类号： G11C29/44
CPC分类号： G11C29/50 , G11C16/04 , G11C29/44 , G11C29/50004
摘要： A memory device including a cell array is disclosed. One embodiment includes a plurality of memory cells, wherein each memory cell is capable of showing at least two distinguishable states, a programmable read voltage source adapted to supply an alterable read voltage and a test control unit. The test control unit includes a voltage control unit that is capable of controlling the read voltage source, a counter unit that is capable of counting the memory cells exhibiting a predetermined state and an analysis unit that is capable of rating a currently determined number of memory cells exhibiting a predetermined state.
摘要翻译：公开了一种包括单元阵列的存储器件。一个实施例包括多个存储器单元，其中每个存储器单元能够显示至少两个可区分状态，适于提供可变读取电压的可编程读取电压源和测试控制单元。测试控制单元包括能够控制读取电压源的电压控制单元，能够对呈现预定状态的存储单元进行计数的计数单元和能够对当前确定数量的存储单元进行评级的分析单元呈现预定状态。

6. 发明授权

US07403438B2 Memory array architecture and method for high-speed distribution measurements 有权
公开(公告)号：US07403438B2
公开(公告)日：2008-07-22
申请号：US11485185
申请日：2006-07-12
申请人： Volker Zipprich-Rasch
发明人： Volker Zipprich-Rasch
IPC分类号： G11C7/00
CPC分类号： G11C29/44 , G11C29/50 , G11C29/50004
摘要： A method includes an initial process of selecting a memory cell within the memory array and an operating condition under which the memory cell is to be tested. The memory cell is tested under the specified operating condition, and a measured response obtained therefrom. Based upon the measured response, a determination is made as to whether the memory cell passes or fails a predetermined criterion. The pass/fail result is communicated to a counter that is integrated on-chip with the memory array, the counter operable to accumulate a total number of pass or fail results supplied thereto. The aforementioned processes are repeated for at least one different memory cell, whereby the new memory cell is tested under the aforementioned operating conditions. Subsequently, a data value representing the accumulated number of pass or fail results is output from the on-chip counter.

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