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1. 发明授权

US07787370B1 Technique for adaptively load balancing connections in multi-link trunks 有权
标题翻译：多链路干线自适应负载平衡连接技术
公开(公告)号：US07787370B1
公开(公告)日：2010-08-31
申请号：US09946736
申请日：2001-09-06
申请人： James Aweya , Michel Ouellette , Delfin Y. Montuno , Kent Felske
发明人： James Aweya , Michel Ouellette , Delfin Y. Montuno , Kent Felske
IPC分类号： G01R31/08
CPC分类号： H04L47/10 , H04L45/245 , H04L47/125 , Y02D50/30
摘要： A technique for adaptively load balancing connections in multi-link trunks is disclosed. The present invention provides an adaptive load balancing algorithm that utilizes relative link quality metrics to adjust traffic distribution between links. Link quality metrics may include short-term averages of an observed packet drop rate for each member link in a bundle. The present invention may dynamically adjust the number of flows on each link in proportion to available bandwidth. In addition, link quality metrics may be equalized, such that no link is more lossy than the others.
摘要翻译：公开了一种用于在多链路干线中自适应地负载平衡连接的技术。本发明提供一种自适应负载平衡算法，其利用相对链路质量度量来调整链路之间的业务分布。链路质量度量可以包括捆绑中每个成员链路观察到的分组丢弃率的短期平均值。本发明可以与可用带宽成比例地动态地调整每个链路上的流量。此外，链路质量度量可能会相等，使得没有链路比其他链路更有损耗。

2. 发明申请

US20120182863A1 PROTOCOL FOR CLOCK DISTRIBUTION AND LOOP RESOLUTION 失效
标题翻译：时钟分配和环路分辨率协议
公开(公告)号：US20120182863A1
公开(公告)日：2012-07-19
申请号：US13362319
申请日：2012-01-31
申请人： Michel Ouellette , James Aweya , Delfin Y. Montuno , Kent Felske , Michael George Mayer
发明人： Michel Ouellette , James Aweya , Delfin Y. Montuno , Kent Felske , Michael George Mayer
IPC分类号： H04L12/44 , H04L12/26
CPC分类号： H04L41/12 , H04J3/0679
摘要： In response to a network topology change, a clock root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message.
摘要翻译：响应于网络拓扑变化，时钟根节点通过构建时钟源拓扑树来为每个受影响的节点计算新的时钟路径，并且从该树中识别来自较高或相等层次的时钟源的网络节点的路径到该网络节点。根节点然后向每个节点发送一个网络消息，指示节点应该使用的新路径。每个节点接收消息，并将新路径与现有路径进行比较。如果路径不同，则节点获取刚刚在消息中接收到的新路径。如果路径相同，则节点不执行任何操作并丢弃该消息。

3. 发明授权

US07656985B1 Timestamp-based all digital phase locked loop for clock synchronization over packet networks 有权
标题翻译：基于时间戳的全数字锁相环，用于通过分组网络进行时钟同步
公开(公告)号：US07656985B1
公开(公告)日：2010-02-02
申请号：US11279431
申请日：2006-04-12
申请人： James Aweya , Michel Ouellette , Delfin Y. Montuno , Kent Felske
发明人： James Aweya , Michel Ouellette , Delfin Y. Montuno , Kent Felske
IPC分类号： H03D3/24
CPC分类号： H03L7/093 , H03L7/0992 , H03L7/18 , H04J3/0632 , H04J3/0664
摘要： A timestamp-based all digital phase locked loop is utilized for clock synchronization for Circuit Emulation Service (“CES”) over packet networks. The all digital phase locked loop at a CES receiver includes a phase detector, a loop filter, a digital oscillator and a timestamp counter. The all digital phase locked loop enables the CES receiver to synchronize a local clock at the receiver with a clock at a CES transmitter, where indications of transmitter clock signals are communicated to the receiver as timestamps. The phase detector is operable to compute an error signal indicative of differences between the timestamps and a local clock signal. The loop filter is operable to reduce jitter and noise in the error signal, and thereby produce a control signal. The digital oscillator is operable to oscillate at a frequency based at least in-part on the control signal, and thereby produce a digital oscillator output signal. The timestamp counter operable to count pulses in the digital oscillator output signal, and output the local clock signal.
摘要翻译：基于时间戳的全数字锁相环用于通过分组网络进行电路仿真服务（“CES”）的时钟同步。 CES接收机的全数字锁相环包括相位检测器，环路滤波器，数字振荡器和时间戳计数器。全数字锁相环使得CES接收机能够使接收机处的本地时钟与CES发射机的时钟同步，其中发射机时钟信号的指示作为时间戳传送到接收机。相位检测器可用于计算指示时间戳与本地时钟信号之间的差异的误差信号。环路滤波器可操作以减少误差信号中的抖动和噪声，从而产生控制信号。数字振荡器可操作以至少部分地基于控制信号以频率振荡，从而产生数字振荡器输出信号。时间戳计数器可用于对数字振荡器输出信号中的脉冲进行计数，并输出本地时钟信号。

4. 发明授权

US08755308B2 Protocol for clock distribution and loop resolution 失效
标题翻译：时钟分配和循环分辨率协议
公开(公告)号：US08755308B2
公开(公告)日：2014-06-17
申请号：US13362319
申请日：2012-01-31
申请人： Michel Ouellette , James Aweya , Delfin Y. Montuno , Kent Felske , Michael George Mayer
发明人： Michel Ouellette , James Aweya , Delfin Y. Montuno , Kent Felske , Michael George Mayer
IPC分类号： H04L12/28
CPC分类号： H04L41/12 , H04J3/0679
摘要： In response to a network topology change, a clock root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message.
摘要翻译：响应于网络拓扑变化，时钟根节点通过构建时钟源拓扑树来计算每个受影响节点的新时钟路径，并且从该树中识别来自较高或相等层次的时钟源的网络节点的路径到该网络节点。根节点然后向每个节点发送一个网络消息，指示该节点应该使用的新路径。每个节点接收消息，并将新路径与现有路径进行比较。如果路径不同，则节点获取刚刚在消息中接收到的新路径。如果路径相同，则节点不执行任何操作并丢弃该消息。

5. 发明授权

US08125930B2 Protocol for clock distribution and loop resolution 失效
标题翻译：时钟分配和循环分辨率协议
公开(公告)号：US08125930B2
公开(公告)日：2012-02-28
申请号：US11609966
申请日：2006-12-13
申请人： Michel Ouellette , James Aweya , Delfin Y. Montuno , Kent Felske
发明人： Michel Ouellette , James Aweya , Delfin Y. Montuno , Kent Felske
IPC分类号： H04L12/28
CPC分类号： H04L41/12 , H04J3/0679
摘要： Algorithms and data structure are described for constructing and maintaining a clock distribution tree (“CDT”) for timing loop avoidance. The CDT algorithms and data structure allows a node to make an automated and unattended path switch to the most desirable clock source in the network. In response to a network topology change, a clock root node distributes new clock paths to all nodes in the network. In particular, the root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message.
摘要翻译：描述了用于构建和维护用于定时回路的时钟分布树（“CDT”）的算法和数据结构。 CDT算法和数据结构允许节点将自动和无人值守的路径切换到网络中最理想的时钟源。响应于网络拓扑变化，时钟根节点将新的时钟路径分配给网络中的所有节点。特别地，根节点通过构建时钟源拓扑树来计算每个受影响节点的新时钟路径，并且从该树中识别来自相对于该网络节点的较高或相等层的时钟源到网络节点的路径。根节点然后向每个节点发送一个网络消息，指示节点应该使用的新路径。每个节点接收消息，并将新路径与现有路径进行比较。如果路径不同，则节点获取刚刚在消息中接收到的新路径。如果路径相同，则节点不执行任何操作并丢弃该消息。

6. 发明授权

US07860205B1 Clock synchronization using a weighted least squares error filtering technique 有权
标题翻译：使用加权最小二乘法误差滤波技术的时钟同步
公开(公告)号：US07860205B1
公开(公告)日：2010-12-28
申请号：US11279410
申请日：2006-04-12
申请人： James Aweya , Michel Ouellette , Delfin Y. Montuno , Kent Felske
发明人： James Aweya , Michel Ouellette , Delfin Y. Montuno , Kent Felske
IPC分类号： H03D3/24
CPC分类号： H03L7/093 , H03L7/0992 , H03L7/0994 , H03L7/18 , H04J3/0632 , H04J3/0664 , H04N21/242 , H04N21/4305 , H04N21/64322 , H04N21/8547
摘要： A timestamp-based clock synchronization technique is employed for CES in packet networks. The technique is based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behavior of clock synchronization errors between a transmitter and a receiver. The technique is particularly suitable for clock synchronization in networks where the transmitter and receiver are not driven from a common timing reference but the receiver requires timing reference traceable to the transmitter clock.
摘要翻译：基于时间戳的时钟同步技术用于分组网络中的CES。该技术基于双指数滤波技术和线性过程模型。线性过程模型用于描述发射机和接收机之间的时钟同步误差的行为。该技术特别适用于发射机和接收机不从公共定时参考驱动的网络中的时钟同步，但是接收机需要可追溯到发射机时钟的定时参考。

7. 发明授权

US07643595B2 Method and apparatus for synchronizing clock timing between network elements 有权
标题翻译：用于在网络元件之间同步时钟定时的方法和装置
公开(公告)号：US07643595B2
公开(公告)日：2010-01-05
申请号：US11172335
申请日：2005-06-30
申请人： James Aweya , Delfin Y. Montuno , Michel Ouellette , Kent Felske
发明人： James Aweya , Delfin Y. Montuno , Michel Ouellette , Kent Felske
IPC分类号： H04L7/00 , H04D3/04
CPC分类号： H03L7/0805 , H03D13/002 , H03L7/085 , H03L7/093 , H03L7/0992 , H03L7/10 , H03L2207/50 , H04J3/0658 , H04J3/0664
摘要： Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).
摘要翻译：网络元件可以通过将主时钟实现为包括数字控制频率选择器（DCFS）的全数字PLL的主时钟同步，其输出频率可以通过控制字的输入直接控制。 PLL会导致对主DCFS的输入控制字进行调整，使主DCFS的输出锁定在参考频率上。与控制字相关的信息从主时钟发送到也被实现为DCFS的从时钟。通过使用所发送的信息来重建主控制字，可以使从属设备呈现与主DCFS相同的状态，而不需要将从机实现为PLL。 DCFS可以形成为数字控制振荡器（DCO）或直接数字合成器（DDS）。

8. 发明授权

US07528776B2 Beacon-assisted precision location of untethered client in packet networks 失效
标题翻译：分组网络中无信号客户端的信标辅助精确定位
公开(公告)号：US07528776B2
公开(公告)日：2009-05-05
申请号：US11689660
申请日：2007-03-22
申请人： Delfin Y. Montuno , James Aweya , Michel Ouellette , Kent Felske
发明人： Delfin Y. Montuno , James Aweya , Michel Ouellette , Kent Felske
IPC分类号： G01S3/02
CPC分类号： G01S5/06
摘要： A novel beacon-based position location technique for efficient location discovery of untethered clients in packet networks is disclosed. The position location technique utilizes the time-difference-of-arrival (“TDOA”) of a first signal transmitted by a beacon of known location and a second signal transmitted by an untethered client. The TDOA of these two signals is measured locally by at least three non-collinear signal receivers. For each of the receivers, the TDOA is used to calculate a perceived distance to the client. A circle is then calculated for each receiver, centered on the receiver and having a radius equal to the perceived distance. At least two lines defined by points of intersection of the calculated circles are then calculated. The point of intersection of the lines represents the location of the client. To facilitate operation, the signal receivers may be arranged on vertices which define a convex polygon as viewed from above. The location system requires no time (time-of-day) synchronization of the signal receivers, and only the coarse frequency synchronization, on the order of, tens of parts-per-million (ppm). The technique even works for the case where the signal receivers are run asynchronously, provided the frequency accuracies of the signal receivers are on the order of about 50 ppm or better. The technique introduces no communication overhead for the beacon, client and signal receivers. Further, the computation overhead at the signal receivers is relatively low because the location detection algorithm involves only simple algebraic operations over scalar values.
摘要翻译：公开了一种新颖的基于信标的位置定位技术，用于在分组网络中无阻塞客户端的有效位置发现。位置定位技术利用由已知位置的信标发送的第一信号的到达时间差（“TDOA”）和由无阻塞客户端发送的第二信号。这两个信号的TDOA由至少三个非共线信号接收器本地测量。对于每个接收机，TDOA用于计算到客户端的感知距离。然后，以接收机为中心并且具有等于感知距离的半径的每个接收机计算一个圆。然后计算由计算圆的交点定义的至少两条线。线的交点表示客户端的位置。为了便于操作，信号接收器可以被布置在从上方观察的限定凸多边形的顶点上。定位系统不需要信号接收机的时间（时间）同步，只需要几十分之一百万分之几的粗略频率同步（ppm）。该技术甚至适用于信号接收机异步运行的情况，只要信号接收机的频率精度在约50 ppm或更高的数量级。该技术不引入信标，客户端和信号接收机的通信开销。此外，信号接收机的计算开销相对较低，因为位置检测算法仅涉及标量值的简单代数运算。

9. 发明授权

US07613268B2 Method and apparatus for designing a PLL 失效
标题翻译：用于设计PLL的方法和设备
公开(公告)号：US07613268B2
公开(公告)日：2009-11-03
申请号：US11394705
申请日：2006-03-31
申请人： James Aweya , Delfin Y. Montuno , Michel Ouellette , Kent Felske
发明人： James Aweya , Delfin Y. Montuno , Michel Ouellette , Kent Felske
IPC分类号： H03D3/24
CPC分类号： H03L7/08 , H03L2207/50
摘要： A method and apparatus for designing a PLL enables initial component characteristics and design specifications of the PLL to be specified. Time constants for a loop filter that would be required to create a PLL having the desired design specifications and component characteristics are then computed. The performance or behavior characteristics of the PLL may then be computed for the PLL given the time constants and the initial set of components, to determine whether the performance of the PLL would be considered satisfactory. For example, PLL design software may determine whether a PLL would be sufficiently stable if it was to be created using the particular selected components given the required design specifications. Where the PLL does not meet particular behavior characteristics, the PLL design software may provide guidance as to what component characteristics would improve performance of the PLL. Designed PLLs may be used for timestamp based clock synchronization.
摘要翻译：用于设计PLL的方法和装置使得能够指定PLL的初始组件特性和设计规范。然后计算创建具有所需设计规范和组件特性的PLL所需的环路滤波器的时间常数。然后可以为给定时间常数和初始组件组的PLL计算PLL的性能或行为特性，以确定PLL的性能是否被认为是令人满意的。例如，PLL设计软件可以确定PLL是否将足够稳定，如果要在给定所需设计规范的情况下使用特定的选定组件创建PLL。在PLL不符合特定行为特性的情况下，PLL设计软件可以提供关于什么组件特性将提高PLL性能的指导。设计的PLL可用于基于时间戳的时钟同步。

10. 发明授权

US07590210B2 Method and apparatus for synchronizing internal state of frequency generators on a communications network 失效
标题翻译：用于使通信网络上的频率发生器的内部状态同步的方法和装置
公开(公告)号：US07590210B2
公开(公告)日：2009-09-15
申请号：US11172100
申请日：2005-06-30
申请人： James Aweya , Delfin Y. Montuno , Michel Ouellette , Kent Felske
发明人： James Aweya , Delfin Y. Montuno , Michel Ouellette , Kent Felske
IPC分类号： H04L7/00 , H04J3/06
CPC分类号： H03L7/0992 , H04J3/0664
摘要： A first level of control over operation of slave Digitally Controlled Frequency Selectors (DCFSs), such as DCOs or DDSs, may occur by periodic transmission of control words from the master clock to the slave clocks. To allow enhanced control over the output of the slave clocks, the frequency of the local oscillator used to generate the synthesized output of the master clock may also be conveyed to the slave clocks to allow a second level of control to take place. The second level of control allows the local oscillators at the slave clocks to lock onto the frequency of the master local oscillator to thereby allow the slave local oscillators to operate the slave DCFSs using the same local oscillator frequency. The first level of control synchronizes operation of the DCFSs while the second level control prevents instabilities in the local oscillators from causing long term drift between the slave and master clock outputs. Timestamps may be used to synchronize the master and slave local oscillators.
摘要翻译：通过从主时钟到从时钟的控制字的周期性传输，可能会发生对从属数字控制频率选择器（DCFS）（如DCO或DDS）的操作的第一级控制。为了增强对从时钟的输出的控制，用于产生主时钟的合成输出的本地振荡器的频率也可以被传送到从时钟，以允许进行第二级控制。第二级控制允许从时钟的本地振荡器锁定到主本地振荡器的频率，从而允许从局部振荡器使用相同的本地振荡器频率来操作从DCFS。第一级控制同步DCFS的操作，而第二级控制防止本地振荡器中的不稳定性引起从机和主时钟输出之间的长期漂移。时间戳可用于同步主从本地振荡器。

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