专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140003147A1 Optimized Erase Operation For Non-Volatile Memory With Partially Programmed Block 有权
标题翻译：用于部分编程块的非易失性存储器的优化擦除操作
公开(公告)号：US20140003147A1
公开(公告)日：2014-01-02
申请号：US13537551
申请日：2012-06-29
申请人： Deepanshu Dutta , Ken Oowada , Koichi Nishimura , Yingda Dong
发明人： Deepanshu Dutta , Ken Oowada , Koichi Nishimura , Yingda Dong
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C11/5635 , G11C16/16 , G11C16/344
摘要： In connection with an erase operation of a block of non-volatile storage elements, a determination is made as to whether the block is partially but not fully programmed. A degree of partial programming can be determined by a pre-erase read operation which determines a highest programmed word line, or which determines whether there is a programmed storage element in a subset of word lines above a small subset of source side word lines. Since a partially programmed block will pass an erase-verify test more easily than a fully programmed block, a measure is taken to ensure that the block is sufficiently deeply erased. In one approach, an erase-verify test is made stricter by adjusting a sensing parameter when the block is partially programmed. In another approach, the block can be programmed before being erased. Or, an extra erase pulse which is not followed by an erase-verify test can be applied.
摘要翻译：关于非易失性存储元件块的擦除操作，确定块是部分地还是不完全编程的。部分编程的程度可以通过确定最高编程字线的预擦除读取操作来确定，或者确定在源侧字线的小子集之上的字线子集中是否存在编程存储元件。由于部分编程的块将比完全编程的块更容易通过擦除验证测试，因此采取措施确保块被深度擦除。在一种方法中，通过在块被部分编程时调整感测参数，擦除验证测试变得更严格。在另一种方法中，块可以被擦除之前被编程。或者，可以应用不跟随擦除验证测试的额外擦除脉冲。

2. 发明授权

US08787088B2 Optimized erase operation for non-volatile memory with partially programmed block 有权
标题翻译：具有部分编程块的非易失性存储器的优化擦除操作
公开(公告)号：US08787088B2
公开(公告)日：2014-07-22
申请号：US13537551
申请日：2012-06-29
申请人： Deepanshu Dutta , Ken Oowada , Koichi Nishimura , Yingda Dong
发明人： Deepanshu Dutta , Ken Oowada , Koichi Nishimura , Yingda Dong
IPC分类号： G11C11/34
CPC分类号： G11C11/5635 , G11C16/16 , G11C16/344
摘要： In connection with an erase operation of a block of non-volatile storage elements, a determination is made as to whether the block is partially but not fully programmed. A degree of partial programming can be determined by a pre-erase read operation which determines a highest programmed word line, or which determines whether there is a programmed storage element in a subset of word lines above a small subset of source side word lines. Since a partially programmed block will pass an erase-verify test more easily than a fully programmed block, a measure is taken to ensure that the block is sufficiently deeply erased. In one approach, an erase-verify test is made stricter by adjusting a sensing parameter when the block is partially programmed. In another approach, the block can be programmed before being erased. Or, an extra erase pulse which is not followed by an erase-verify test can be applied.
摘要翻译：关于非易失性存储元件块的擦除操作，确定块是部分地还是不完全编程的。可通过预擦除读取操作来确定部分编程的程度，该擦除读取操作确定最高编程字线，或者确定在源侧字线的小子集之上的字线子集中是否存在编程存储元件。由于部分编程的块将比完全编程的块更容易通过擦除验证测试，因此采取措施确保块被深度擦除。在一种方法中，通过在块被部分编程时调整感测参数，擦除验证测试变得更严格。在另一种方法中，块可以被擦除之前被编程。或者，可以应用不跟随擦除验证测试的额外擦除脉冲。

3. 发明申请

US20110242899A1 EXTRA DUMMY ERASE PULSES AFTER SHALLOW ERASE-VERIFY TO AVOID SENSING DEEP ERASED THRESHOLD VOLTAGE 有权
标题翻译：经过擦除后的额外消除脉冲可以避免感测深度电压阈值电压
公开(公告)号：US20110242899A1
公开(公告)日：2011-10-06
申请号：US12751265
申请日：2010-03-31
申请人： Ken Oowada , Yingda Dong , Deepanshu Dutta
发明人： Ken Oowada , Yingda Dong , Deepanshu Dutta
IPC分类号： G11C16/04 , G11C16/14 , G11C16/06
CPC分类号： G11C11/5635 , G11C16/14 , G11C16/3436
摘要： An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify operation. The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached, at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes. The second phase applies one or more extra erase pulses which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write-erase endurance, while still achieving the desired deep erase.
摘要翻译：用于非易失性存储器的擦除操作包括第一和第二相。第一阶段将一系列电压脉冲施加到衬底，其中每个擦除脉冲之后是验证操作。验证操作使用从最终期望的阈值电压电平偏移的验证电平。擦除脉冲以幅度升高直到达到最大电平，此时施加最大电平的附加擦除脉冲。当验证操作通过时，第一阶段结束。第二阶段施加一个或多个额外的擦除脉冲，其幅度高于第一阶段中的最后一个擦除脉冲，并且其后跟无验证操作。这避免了在深的负阈值电压电平下执行验证操作的需要，这可能导致电荷捕获，从而减少写擦除耐久性，同时仍然实现期望的深度擦除。

4. 发明授权

US08130551B2 Extra dummy erase pulses after shallow erase-verify to avoid sensing deep erased threshold voltage 有权
标题翻译：进行浅擦除验证后的额外的虚拟擦除脉冲，以避免感测深度擦除的阈值电压
公开(公告)号：US08130551B2
公开(公告)日：2012-03-06
申请号：US12751265
申请日：2010-03-31
申请人： Ken Oowada , Yingda Dong , Deepanshu Dutta
发明人： Ken Oowada , Yingda Dong , Deepanshu Dutta
IPC分类号： G11C16/04
CPC分类号： G11C11/5635 , G11C16/14 , G11C16/3436
摘要： An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify operation. The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached, at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes. The second phase applies one or more extra erase pulses which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write-erase endurance, while still achieving the desired deep erase.
摘要翻译：用于非易失性存储器的擦除操作包括第一和第二相。第一阶段将一系列电压脉冲施加到衬底，其中每个擦除脉冲之后是验证操作。验证操作使用从最终期望的阈值电压电平偏移的验证电平。擦除脉冲以幅度升高直到达到最大电平，此时施加最大电平的附加擦除脉冲。当验证操作通过时，第一阶段结束。第二阶段施加一个或多个额外的擦除脉冲，其幅度高于第一阶段中的最后一个擦除脉冲，并且其后跟无验证操作。这避免了在深的负阈值电压电平下执行验证操作的需要，这可能导致电荷捕获，从而减少写擦除耐久性，同时仍然实现期望的深度擦除。

5. 发明授权

US08081514B2 Partial speed and full speed programming for non-volatile memory using floating bit lines 有权
标题翻译：使用浮动位线对非易失性存储器进行部分速度和全速编程
公开(公告)号：US08081514B2
公开(公告)日：2011-12-20
申请号：US12547449
申请日：2009-08-25
申请人： Man Mui , Yingda Dong , Binh Lee , Deepanshu Dutta
发明人： Man Mui , Yingda Dong , Binh Lee , Deepanshu Dutta
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.
摘要翻译：非易失性存储器系统实现了部分速度和全速编程。在编程操作期间，在第一时间段中，要禁止的存储元件的位线被预充电，而要以部分速度编程的存储元件的位线和要全速编程的存储元件的位线是固定的在第二时间段中，以部分速度编程的存储元件的位线被驱动得较高，而待禁止的存储元件的位线被浮置，并且待编程的存储元件的位线保持固定。在第三时间段中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

6. 发明授权

US07800956B2 Programming algorithm to reduce disturb with minimal extra time penalty 有权
标题翻译：编程算法以最小的额外时间损失来减少干扰
公开(公告)号：US07800956B2
公开(公告)日：2010-09-21
申请号：US12163073
申请日：2008-06-27
申请人： Dana Lee , Deepanshu Dutta , Yingda Dong
发明人： Dana Lee , Deepanshu Dutta , Yingda Dong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
摘要翻译：在多遍编程过程中，非易失性存储器中的编程时间会减少。在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

7. 发明授权

US07876611B2 Compensating for coupling during read operations in non-volatile storage 有权
标题翻译：补偿在非易失性存储器中读取操作期间的耦合
公开(公告)号：US07876611B2
公开(公告)日：2011-01-25
申请号：US12188629
申请日：2008-08-08
申请人： Deepanshu Dutta , Jeffrey W. Lutze , Yingda Dong , Henry Chin , Toru Ishigaki
发明人： Deepanshu Dutta , Jeffrey W. Lutze , Yingda Dong , Henry Chin , Toru Ishigaki
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3418
摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.
摘要翻译：通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压字线。当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据相邻存储元件。

8. 发明申请

US20110051517A1 PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES 有权
标题翻译：使用浮动位线的非易失性存储器的部分速度和全速编程
公开(公告)号：US20110051517A1
公开(公告)日：2011-03-03
申请号：US12547449
申请日：2009-08-25
申请人： Man Mui , Yingda Dong , Binh Le , Deepanshu Dutta
发明人： Man Mui , Yingda Dong , Binh Le , Deepanshu Dutta
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.
摘要翻译：非易失性存储器系统实现了部分速度和全速编程。在编程操作期间，在第一时间段中，要禁止的存储元件的位线被预充电，而要以部分速度编程的存储元件的位线和要全速编程的存储元件的位线是固定的在第二时间段中，以部分速度编程的存储元件的位线被驱动得较高，而待禁止的存储元件的位线被浮置，并且待编程的存储元件的位线保持固定。在第三时间段中，待被禁止的存储元件的位线被驱动得较高，而以部分速度或全速编程的存储元件的位线被浮动，使得它们耦合得更高。

9. 发明申请

US20100034022A1 COMPENSATING FOR COUPLING DURING READ OPERATIONS IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中读取操作期间的耦合补偿
公开(公告)号：US20100034022A1
公开(公告)日：2010-02-11
申请号：US12188629
申请日：2008-08-08
申请人： Deepanshu Dutta , Jeffrey W. Lutze , Yingda Dong , Henry Chin , Toru Ishigaki
发明人： Deepanshu Dutta , Jeffrey W. Lutze , Yingda Dong , Henry Chin , Toru Ishigaki
IPC分类号： G11C16/06
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/3418
摘要： Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.
摘要翻译：通过调整施加到相邻位线的电压来补偿相邻位线上的存储元件的电容耦合。执行初始粗略读取以确定位线相邻存储元件的数据状态，并且在随后的精细读取期间，基于确定的状态和施加到所选择的电流控制栅极读取电压的电流控制栅极读取电压来设置位线电压字线。当电流控制栅极读取电压对应于比相邻存储元件的确定状态低的数据状态时，使用补偿位线电压。也可以通过对相邻字线应用不同的读通过电压来提供来自相邻字线上的存储元件的耦合的补偿，并且使用基于字线的数据状态来识别的特定读通过电压来获得读取数据相邻的存储元件。

10. 发明申请

US20090323429A1 PROGRAMMING ALGORITHM TO REDUCE DISTURB WITH MINIMAL EXTRA TIME PENALTY 有权
标题翻译：使用最小额外罚款减少差距的编程算法
公开(公告)号：US20090323429A1
公开(公告)日：2009-12-31
申请号：US12163073
申请日：2008-06-27
申请人： Dana Lee , Deepanshu Dutta , Yingda Dong
发明人： Dana Lee , Deepanshu Dutta , Yingda Dong
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Programming time is reduced in a non-volatile memory in a multi-pass programming process. In a first programming pass, high state cells are programmed by a sequence of program pulses to identify fast and slow high state cells, while lower state cells are locked out from programming. Once identified, the fast high state cells are temporarily locked out from programming while the slow high state cells continue being programmed to their final intended state. Further, the program pulses are sharply stepped up to program the slow high state cells. In a second programming pass, the fast high state cells are programmed along with the other, lower state cells, until they all reach their respective intended states. A time savings is realized compared to approaches in which all high state cells are programmed in the first programming pass.
摘要翻译：在多遍编程过程中，非易失性存储器中的编程时间会减少。在第一编程通道中，高状态单元通过一系列编程脉冲进行编程，以识别快速和慢速的高状态单元，而较低状态单元被从编程中锁定。一旦识别，快速高状态单元暂时被禁止编程，而缓慢的高状态单元继续被编程到其最终预期状态。此外，编程脉冲急剧地升高以对慢速高状态单元进行编程。在第二个编程过程中，快速高状态单元与其他较低状态单元一起编程，直到它们都达到各自的预期状态。与在第一编程通路中编程所有高状态单元的方法相比，实现了时间节省。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式