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1. 发明授权

US08886874B1 System and method for low-latency addressing in flash memory 有权
标题翻译：闪存中低延迟寻址的系统和方法
公开(公告)号：US08886874B1
公开(公告)日：2014-11-11
申请号：US13925807
申请日：2013-06-24
申请人： Deboleena Minz Sakalley , Rakesh Pandey
发明人： Deboleena Minz Sakalley , Rakesh Pandey
IPC分类号： G06F12/04 , G11C16/32 , G11C16/08
CPC分类号： G06F12/0246 , G06F2212/1024 , G06F2212/7201 , G06F2212/7202
摘要： A system for operating a flash memory includes a memory controller in communication with a processor. The memory controller includes a memory read access command receiver that receives a memory read access command from the processor. The memory read access command includes a memory cell address of a memory cell to be accessed for the execution of the memory read accessed command. The memory cell address includes a current sector address and a sector specific memory cell address. The flash memory is provided with either both the current sector address and the sector specific memory cell address or only the sector specific memory cell address for generating the memory cell address.
摘要翻译：用于操作闪速存储器的系统包括与处理器通信的存储器控制器。存储器控制器包括从处理器接收存储器读取访问命令的存储器读访问命令接收器。存储器读取访问命令包括要访问以存储器读取访问命令的执行的存储器单元的存储器单元地址。存储单元地址包括当前扇区地址和扇区特定存储单元地址。闪速存储器既提供当前扇区地址和扇区特定存储单元地址，也可以仅提供用于生成存储单元地址的扇区特定存储单元地址。

2. 发明授权

US09142280B1 Circuit for configuring external memory 有权
标题翻译：用于配置外部存储器的电路
公开(公告)号：US09142280B1
公开(公告)日：2015-09-22
申请号：US14452536
申请日：2014-08-06
申请人： Rakesh Pandey , Bharat K. Kumbhkar , Biswaprakash Navajeevan , Manmohan Rana
发明人： Rakesh Pandey , Bharat K. Kumbhkar , Biswaprakash Navajeevan , Manmohan Rana
IPC分类号： G11C7/00 , G11C11/406 , G11C11/4074 , G11C11/4093 , G11C11/4094
CPC分类号： G11C11/40615 , G11C11/4074 , G11C11/4093 , G11C11/4094 , G11C2211/4067
摘要： A circuit for configuring an external memory includes a memory controller, a register, an OR gate, first and second input/output (IO) pads, and pull-up and pull-down resistors. When the circuit is in a high power mode, the memory controller refreshes the external memory by providing reset and clock enable signals to the external memory by way of the first and second IO pads. When the circuit is in a low power mode, the pull-up and pull-down resistors configure the external memory in a self-refresh mode. When the circuit exits the low power mode, the first and second IO pads are powered on. The OR gate receives and provides a control signal output by the register to the external memory by way of the first IO pad, which keeps the external memory in the self-refresh mode.
摘要翻译：用于配置外部存储器的电路包括存储器控制器，寄存器，或门，第一和第二输入/输出（IO）焊盘以及上拉和下拉电阻。当电路处于高功率模式时，存储器控制器通过第一和第二IO焊盘向外部存储器提供复位和时钟使能信号来刷新外部存储器。当电路处于低功耗模式时，上拉和下拉电阻将自身刷新模式下的外部存储器配置。当电路退出低功耗模式时，第一个和第二个IO焊盘通电。或门通过第一个IO接口接收寄存器输出的控制信号到外部存储器，保持外部存储器处于自刷新模式。

3. 发明授权

US09053325B2 Decryption key management system 有权
标题翻译：解密密钥管理系统
公开(公告)号：US09053325B2
公开(公告)日：2015-06-09
申请号：US13972933
申请日：2013-08-22
申请人： Mohit Arora , Rakesh Pandey
发明人： Mohit Arora , Rakesh Pandey
IPC分类号： G06F9/00 , G06F15/177 , G06F21/57 , H04L9/08
CPC分类号： G06F21/575 , H04L9/08 , H04L9/0863 , H04L9/3228
摘要： A decryption key management system includes a memory, a memory controller, a decryption engine, and an on-chip crypto-accelerator. A key blob and an encrypted code are stored in the memory. The memory controller fetches the key blob and stores it in a memory buffer. The decryption engine fetches the key blob and decrypts it using an OTP key to generate a decryption key. The decryption key is used to decrypt the encrypted code and generate a decrypted code.
摘要翻译：解密密钥管理系统包括存储器，存储器控制器，解密引擎和片上加密加速器。密钥块和加密代码存储在存储器中。内存控制器提取密钥blob并将其存储在内存缓冲区中。解密引擎使用OTP密钥取出密钥库并对其进行解密，以生成解密密钥。解密密钥用于解密加密代码并生成解密码。

4. 发明申请

US20120045140A1 IMAGE PROCESSING APPARATUS HAVING CONTEXT MEMORY CONTROLLER 有权
标题翻译：具有内容控制器的图像处理装置
公开(公告)号：US20120045140A1
公开(公告)日：2012-02-23
申请号：US13287666
申请日：2011-11-02
申请人： Amit Joshi , Akash Sood , Rakesh Pandey
发明人： Amit Joshi , Akash Sood , Rakesh Pandey
IPC分类号： G06K9/36
CPC分类号： G06T15/005 , G06T2200/28 , H04N1/41 , H04N19/423 , H04N19/91
摘要： An apparatus for use in image processing is set forth that comprises a pixel processor, context memory, and a context memory controller. The pixel processor is adapted to execute a pixel processing operation on a target pixel using a context of the target pixel. The context memory is adapted to store context values associated with the target pixel. The context memory controller may be adapted to control communication of context values between the pixel processor and the context memory. Further, the context memory controller may be responsive to a context initialization signal or the like provided by the pixel processor to initialize the content of the context memory to a known state, even before the pixel processor has completed its image processing operations and/or immediately after completion of its image processing operations. In one embodiment, the pixel processor executes a JBIG coding operation on the target pixel.
摘要翻译：提出了一种用于图像处理的装置，其包括像素处理器，上下文存储器和上下文存储器控制器。像素处理器适于使用目标像素的上下文来对目标像素执行像素处理操作。上下文存储器适于存储与目标像素相关联的上下文值。上下文存储器控制器可以适于控制像素处理器和上下文存储器之间的上下文值的通信。此外，即使在像素处理器完成其图像处理操作之前和/或立即，上下文存储器控制器可以响应由像素处理器提供的上下文初始化信号等将上下文存储器的内容初始化为已知状态完成图像处理操作后。在一个实施例中，像素处理器对目标像素执行JBIG编码操作。

5. 发明申请

US20160033567A1 CRYSTAL OSCILLATOR MONITORING CIRCUIT 有权
标题翻译：水晶振荡器监测电路
公开(公告)号：US20160033567A1
公开(公告)日：2016-02-04
申请号：US14451404
申请日：2014-08-04
申请人： Nishant Singh Thakur , Rakesh Pandey , Manmohan Rana
发明人： Nishant Singh Thakur , Rakesh Pandey , Manmohan Rana
IPC分类号： G01R31/28 , H03B5/32
CPC分类号： G01R31/282 , G01R31/2824 , H03B5/32
摘要： In an integrated circuit, a clock monitor circuit detects when an analog clock signal output by an on-chip crystal oscillator has stabilized. The clock monitor circuit uses an envelope follower circuit to monitor the envelope of the analog clock signal and compare the amplitude of the envelope with a predetermined amplitude value. When the predetermined value is reached and the envelope has remained steady for a predetermined time, an oscillator okay signal is generated. If an oscillator okay signal is not detected within another predetermined time, then an oscillator failure signal may be generated.
摘要翻译：在集成电路中，时钟监视电路检测由片上晶体振荡器输出的模拟时钟信号何时稳定。时钟监视电路使用包围跟踪器电路来监视模拟时钟信号的包络，并将包络的幅度与预定的振幅值进行比较。当达到预定值并且信封在预定时间内保持稳定时，产生振荡器良好信号。如果在另一预定时间内没有检测到振荡器正常信号，则可能产生振荡器故障信号。

6. 发明申请

US20150214167A1 SEMICONDUCTOR DIE WITH VARIABLE LENGTH BOND PAD 审中-公开
标题翻译：具有可变长度粘结垫的SEMICONDUCTOR DIE
公开(公告)号：US20150214167A1
公开(公告)日：2015-07-30
申请号：US14164249
申请日：2014-01-26
申请人： Rishi Bhooshan , Sachin Kalra , Rakesh Pandey , Dzung T. Tran
发明人： Rishi Bhooshan , Sachin Kalra , Rakesh Pandey , Dzung T. Tran
IPC分类号： H01L23/00
CPC分类号： H01L24/06 , H01L24/05 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/0603 , H01L2224/06151 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor die has elongate, adjacent external interface cells that form an interface cell row. Each of the external interface cells provides an external interface for a circuit node of the die. Bond pads are disposed on a surface of the die, with each of the bond pads being electrically connected to a directly underlying one of the interface cells of the interface cell row. Each of the bond pads has a longitudinal axis aligned with a lengthwise axis of its respective directly underlying interface cell. Each of the bond pads also has a multiple potential wire bond site locations along its respective longitudinal axes.
摘要翻译：半导体管芯具有形成界面单元行的细长的相邻外部接口单元。每个外部接口单元为芯片的电路节点提供外部接口。接合焊盘设置在管芯的表面上，其中每个接合焊盘电连接到接口单元行的接口单元的直接下面的一个。每个接合焊盘具有与其相应的直接下面的接口单元的纵向轴线对准的纵向轴线。每个接合焊盘还沿着其各自的纵向轴线具有多个潜在的焊线位置位置。

7. 发明申请

US20150067275A1 SINGLE PORT MEMORY THAT EMULATES DUAL PORT MEMORY 有权
标题翻译：单端口存储器模拟双端口存储器
公开(公告)号：US20150067275A1
公开(公告)日：2015-03-05
申请号：US14016125
申请日：2013-09-01
申请人： Aarul Jain , Rakesh Pandey , Rohit S. Patel
发明人： Aarul Jain , Rakesh Pandey , Rohit S. Patel
IPC分类号： G11C7/10
CPC分类号： G11C7/1075
摘要： A single-port memory that operates in single-cycle dual-port mode has a logical capacity of N=k·m memory words and (k+1) single-port RAM having an overall physical capacity of (k+1)·m memory words. A status register holds words identifying which RAM bank has the last data at the ith address in the RAM banks and defining k status words for valid data among the (k+1) RAM banks. Write data is written to the write address of a valid RAM bank for a write operation in the absence of RAM bank read address contention. Write data is written to the write address of a different RAM bank that has no valid data for a write operation if there is contention with the RAM bank read address RADDR of a read operation. The status register is updated to identify the RAM bank of the write operation.
摘要翻译：在单周期双端口模式下运行的单端口存储器具有N = k·m个存储字的逻辑容量和具有总体物理容量（k + 1）·m的（k + 1）个单端口RAM 记忆词状态寄存器保存识别哪个RAM组具有在RAM组中的第i个地址处的最后数据的字，并且在第（k + 1）个RAM组中定义有效数据的k个状态字。在没有RAM存储体读取地址争用的情况下，将写入数据写入到有效的RAM存储体的写入地址以进行写入操作。如果与读取操作的RAM存储体读取地址RADDR存在冲突，写入数据将被写入到不具有用于写入操作的有效数据的不同RAM存储体的写入地址。更新状态寄存器以识别写入操作的RAM存储区。

8. 发明授权

US08294720B2 Image processing apparatus having context memory controller 有权
标题翻译：具有上下文存储器控制器的图像处理装置
公开(公告)号：US08294720B2
公开(公告)日：2012-10-23
申请号：US13287666
申请日：2011-11-02
申请人： Amit Joshi , Akash Sood , Rakesh Pandey
发明人： Amit Joshi , Akash Sood , Rakesh Pandey
IPC分类号： G06F15/16
CPC分类号： G06T15/005 , G06T2200/28 , H04N1/41 , H04N19/423 , H04N19/91
摘要： An apparatus for use in image processing is set forth that comprises a pixel processor, context memory, and a context memory controller. The pixel processor is adapted to execute a pixel processing operation on a target pixel using a context of the target pixel. The context memory is adapted to store context values associated with the target pixel. The context memory controller may be adapted to control communication of context values between the pixel processor and the context memory. Further, the context memory controller may be responsive to a context initialization signal or the like provided by the pixel processor to initialize the content of the context memory to a known state, even before the pixel processor has completed its image processing operations and/or immediately after completion of its image processing operations. In one embodiment, the pixel processor executes a JBIG coding operation on the target pixel.
摘要翻译：提出了一种用于图像处理的装置，其包括像素处理器，上下文存储器和上下文存储器控制器。像素处理器适于使用目标像素的上下文来对目标像素执行像素处理操作。上下文存储器适于存储与目标像素相关联的上下文值。上下文存储器控制器可以适于控制像素处理器和上下文存储器之间的上下文值的通信。此外，即使在像素处理器完成其图像处理操作之前和/或立即，上下文存储器控制器可以响应由像素处理器提供的上下文初始化信号等将上下文存储器的内容初始化为已知状态完成图像处理操作后。在一个实施例中，像素处理器对目标像素执行JBIG编码操作。

9. 发明授权

US09494987B2 Processing system with low power wake-up pad 有权
标题翻译：具有低功率唤醒垫的处理系统
公开(公告)号：US09494987B2
公开(公告)日：2016-11-15
申请号：US14093473
申请日：2013-11-30
申请人： Dzung T. Tran , Rishi Bhooshan , Rakesh Pandey , Fujio Takeda
发明人： Dzung T. Tran , Rishi Bhooshan , Rakesh Pandey , Fujio Takeda
IPC分类号： G06F1/26 , H01L27/02 , H01L29/06 , G06F1/32 , H01L29/786
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/3287 , H01L27/0222 , H01L29/0611 , H01L29/78609 , Y02D10/171
摘要： An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.
摘要翻译：集成电路包括输入/输出焊盘，输入电路和输出电路。输入电路耦合到输入/输出焊盘，该输入/输出焊盘接收包括唤醒信号的输入信号，该唤醒信号指示集成电路何时从掉电模式切换到活动模式。输出电路耦合到输入/输出焊盘，该输入/输出焊盘向输入/输出焊盘提供输出信号。输出电路包括在阱中的第一P沟道晶体管，其具有耦合到输入/输出焊盘的漏极以及耦合到电源端子的源极。电源端子在活动模式期间接收第一电源电压，并且在掉电模式期间与任何电源解耦。响应于唤醒信号，阱被耦合到唤醒信号，该唤醒信号指示从掉电模式到活动模式的改变。

10. 发明申请

US20150134890A1 MEMORY CONTROLLER, COMPUTING DEVICE WITH A MEMORY CONTROLLER, AND METHOD FOR CALIBRATING DATA TRANSFER OF A MEMORY SYSTEM 有权
标题翻译：存储器控制器，具有存储器控制器的计算装置和用于校准存储器系统的数据传送的方法
公开(公告)号：US20150134890A1
公开(公告)日：2015-05-14
申请号：US14401162
申请日：2012-06-15
申请人： Derek Beattie , Rakesh Pandey , Deboleena Sakalley
发明人： Derek Beattie , Rakesh Pandey , Deboleena Sakalley
IPC分类号： G06F13/42 , G06F12/02
CPC分类号： G06F13/4234 , G06F1/06 , G06F3/0629 , G06F12/0246 , G06F13/1689 , G06F2212/7201 , G11C11/40611 , G11C11/40615 , G11C29/022 , G11C29/028 , G11C2207/2254 , G11C2211/4061
摘要： A memory controller comprises a connection interface connected or connectable to a memory. The memory controller is arranged to read data from the memory via the connection interface The memory controller further comprises a clock unit arranged to provide a data transfer clock signal having a first frequency. The data transfer clock signal may be provided to the memory via the connection interface The data transfer clock signal is arranged for clocking a data transfer from the memory to the memory controller via the connection interface as well as an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an over-sampled calibration data pattern. The second frequency is larger than the first frequency. The memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern.
摘要翻译：存储器控制器包括连接或连接到存储器的连接接口。存储器控制器被布置成经由连接接口从存储器读取数据。存储器控制器还包括布置成提供具有第一频率的数据传输时钟信号的时钟单元。数据传输时钟信号可以经由连接接口提供给存储器。数据传输时钟信号被布置用于经由连接接口对从存储器传送到存储器控制器的数据传输进行计时，以及布置成对校准数据进行采样的过采样电路模式由存储器控制器经由连接接口以第二频率读取以提供过采样的校准数据模式。第二频率大于第一频率。存储器控制器被布置为基于过采样的校准数据模式来确定从存储器到存储器控制器的数据传输的定时偏移。

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