专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08392621B2 Managing dataflow in a temporary memory 失效
标题翻译：在临时内存中管理数据流
公开(公告)号：US08392621B2
公开(公告)日：2013-03-05
申请号：US12820589
申请日：2010-06-22
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F3/00
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/073 , G06F12/0897 , Y02D10/13
摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.
摘要翻译：管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。

2. 发明授权

US08671267B2 Monitoring processing time in a shared pipeline 失效
标题翻译：在共享管道中监视处理时间
公开(公告)号：US08671267B2
公开(公告)日：2014-03-11
申请号：US12822359
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Christine C. Jones , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F9/30 , G06F9/40 , G06F13/00 , G06F3/00
CPC分类号： G06F9/3867 , G06F11/3419 , G06F11/3466 , G06F2201/88
摘要： A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.
摘要翻译：流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。

3. 发明授权

US08522076B2 Error detection and recovery in a shared pipeline 失效
标题翻译：共享管道中的错误检测和恢复
公开(公告)号：US08522076B2
公开(公告)日：2013-08-27
申请号：US12821871
申请日：2010-06-23
申请人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
发明人： Ekaterina M. Ambroladze , Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Diana Lynn Orf , Robert J. Sonnelitter, III
IPC分类号： G06F11/00
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/0793
摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.
摘要翻译：流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。

4. 发明授权

US08327078B2 Dynamic trailing edge latency absorption for fetch data forwarded from a shared data/control interface 失效
标题翻译：从共享数据/控制接口转发的抓取数据的动态后沿延迟吸收
公开(公告)号：US08327078B2
公开(公告)日：2012-12-04
申请号：US12822884
申请日：2010-06-24
申请人： Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0897 , G06F2212/1024
摘要： A computer-implemented method for managing data transfer in a multi-level memory hierarchy that includes receiving a fetch request for allocation of data in a higher level memory, determining whether a data bus between the higher level memory and a lower level memory is available, bypassing an intervening memory between the higher level memory and the lower level memory when it is determined that the data bus is available, and transferring the requested data directly from the higher level memory to the lower level memory.
摘要翻译：一种用于管理多级存储器层级中的数据传输的计算机实现的方法，包括：接收用于在较高级存储器中分配数据的提取请求，确定所述较高级存储器和较低级存储器之间的数据总线是否可用，当确定数据总线可用时，绕过高级存储器和较低级存储器之间的中间存储器，并将所请求的数据直接从较高级存储器传送到下级存储器。

5. 发明授权

US08352687B2 Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy 失效
公开(公告)号：US08352687B2
公开(公告)日：2013-01-08
申请号：US12821726
申请日：2010-06-23
申请人： Deanna Postles Dunn Berger , Michael F. Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
发明人： Deanna Postles Dunn Berger , Michael F. Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state machines and the cache pipe line and is configured to give priority to off chip coherency requests as well as a counter configured to count the number of coherency requests sent from the cache pipeline to a lower level cache. The cache pipeline is halted from sending coherency requests when the counter exceeds a predetermined limit.

6. 发明授权

US09104581B2 eDRAM refresh in a high performance cache architecture 有权
标题翻译： eDRAM在高性能缓存架构中刷新
公开(公告)号：US09104581B2
公开(公告)日：2015-08-11
申请号：US12822245
申请日：2010-06-24
申请人： Michael Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
发明人： Michael Fee , Arthur J. O'Neill, Jr. , Robert J. Sonnelitter, III
IPC分类号： G06F13/14 , G06F12/02 , G06F12/08 , G06F13/16 , G11C11/406
CPC分类号： G06F12/0893 , G06F13/14 , G06F13/16 , G06F13/1605 , G06F13/1636 , G11C11/406 , G11C11/40603 , G11C11/40618 , G11C2207/104
摘要： A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.
摘要翻译：在单个芯片上的存储器刷新请求器，存储器请求解释器，高速缓存存储器和高速缓存控制器。缓存控制器被配置为接收存储器访问请求，对高速缓冲存储器中的存储器地址范围的存储器访问请求，检测位于存储器地址范围的高速缓存存储器可用，并将存储器访问请求发送到存储器请求解释器当存储器地址范围可用时。存储器请求解释器被配置为从高速缓存控制器接收存储器访问请求，确定存储器访问请求是否是刷新存储器地址范围的内容的请求，以及当存储器访问请求是存储器访问请求时刷新存储器地址范围中的数据请求刷新内存。

7. 发明授权

US08495287B2 Clock-based debugging for embedded dynamic random access memory element in a processor core 失效
标题翻译：基于时钟的调试，用于处理器内核中的嵌入式动态随机存取存储器元件
公开(公告)号：US08495287B2
公开(公告)日：2013-07-23
申请号：US12822882
申请日：2010-06-24
申请人： Adam B. Collura , Michael Fee , Arthur J. O'Neill, Jr. , Gerard M. Salem , Robert J. Sonnelitter, III
发明人： Adam B. Collura , Michael Fee , Arthur J. O'Neill, Jr. , Gerard M. Salem , Robert J. Sonnelitter, III
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F11/073 , G06F11/0751
摘要： A method of debugging an embedded dynamic random access memory (eDRAM) element of a processor core is provided. An aspect includes, based on an error occurring in the eDRAM element, stopping a functional clock, and not stopping a refresh clock. Another aspect includes, based on the functional clock being stopped, creating a fence signal that prevents all commands other than a refresh command, the refresh command being based on the refresh clock, from entering into the eDRAM element. Another aspect includes initializing a line fetch controller of the processor core with at least one of write data and read data. Another aspect includes restarting the functional clock. Another aspect includes performing at least one of write requests and read requests to the eDRAM element based on the at least one of the write data and the read data from the line fetch controller based on the functional clock.
摘要翻译：提供了一种调试处理器核心的嵌入式动态随机存取存储器（eDRAM）元件的方法。一个方面包括基于eDRAM元件中发生的错误，停止功能时钟，而不是停止刷新时钟。另一方面包括基于停止的功能时钟，创建围栏信号，该屏障信号防止刷新命令以外的所有命令（刷新命令基于刷新时钟）进入eDRAM元素。另一方面包括用写入数据和读取数据中的至少一个初始化处理器核心的线取指控制器。另一方面包括重启功能时钟。另一方面包括基于功能时钟，基于来自线取指控制器的写入数据和读取数据中的至少一个，向eDRAM元件执行至少一个写入请求和读取请求。

8. 发明授权

US08244972B2 Optimizing EDRAM refresh rates in a high performance cache architecture 失效
标题翻译：在高性能缓存架构中优化EDRAM刷新率
公开(公告)号：US08244972B2
公开(公告)日：2012-08-14
申请号：US12822830
申请日：2010-06-24
申请人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
发明人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0855
摘要： Controlling refresh request transmission rates in a cache comprising: a refresh requestor configured to transmit a refresh request to a cache memory at a first refresh rate, the first refresh rate comprising an interval, the interval comprising receiving a plurality of first signals, the first refresh rate corresponding to a maximum refresh rate, and a refresh counter operatively coupled to the refresh requestor and configured to reset in response to receiving a second signal, increment in response to receiving each of a plurality of refresh requests from the refresh requestor, and reset and transmit a current count to the refresh requestor in response to receiving a third signal, wherein the refresh requestor is configured to transmit a refresh request at a second refresh rate, in response to receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold.
摘要翻译：控制缓存中的刷新请求传输速率包括：刷新请求器，被配置为以第一刷新率向高速缓存存储器发送刷新请求，所述第一刷新率包括间隔，所述间隔包括接收多个第一信号，所述第一刷新速率对应于最大刷新率;以及刷新计数器，可操作地耦合到所述刷新请求器，并且被配置为响应于接收到第二信号而复位，响应于接收到来自所述刷新请求者的多个刷新请求中的每一个，响应于接收到第三信号将当前计数发送到刷新请求者，其中响应于从刷新计数器接收当前计数并确定当前计数，刷新请求器被配置为以第二刷新率发送刷新请求大于刷新阈值。

9. 发明授权

US08645796B2 Dynamic pipeline cache error correction 失效
标题翻译：动态流水线缓存纠错
公开(公告)号：US08645796B2
公开(公告)日：2014-02-04
申请号：US12822437
申请日：2010-06-24
申请人： Ekaterina M. Ambroladze , Michael Fee , Edward T. Gerchman , Arthur J. O'Neill, Jr.
发明人： Ekaterina M. Ambroladze , Michael Fee , Edward T. Gerchman , Arthur J. O'Neill, Jr.
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data.
摘要翻译：动态流水线高速缓存错误校正包括接收执行需要存储高速缓存时隙的操作的请求，存储高速缓冲存储器时隙驻留在高速缓存中。动态流水线高速缓存错误校正还包括访问存储高速缓存时隙，确定存储高速缓存时隙的高速缓存命中，识别和校正与存储高速缓存槽相关联的任何可校正的软错误。动态高速缓存错误校正还包括用校正数据的结果更新高速缓存。

10. 发明授权

US08560767B2 Optimizing EDRAM refresh rates in a high performance cache architecture 失效
标题翻译：在高性能缓存架构中优化EDRAM刷新率
公开(公告)号：US08560767B2
公开(公告)日：2013-10-15
申请号：US13546687
申请日：2012-07-11
申请人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
发明人： Timothy C. Bronson , Michael Fee , Arthur J. O'Neill, Jr. , Scott B. Swaney
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0855
摘要： Embodiments relate to embedded Dynamic Random Access Memory (eDRAM) refresh rates in a high performance cache architecture. An aspect includes receiving a plurality of first signals. A refresh request is transmitted via a refresh requestor to a cache memory at a first refresh rate which includes an interval, including a subset of the first signals. The first refresh rate corresponds to a maximum refresh rate. A refresh counter is reset based on receiving a second signal. The refresh counter is incremented after receiving each of a number of refresh requests. A current count is transmitted from a refresh counter to the refresh requestor based on receiving a third signal. The refresh request is transmitted at a second refresh rate, which is less than the first refresh rate. The refresh request is transmitted based on receiving the current count from the refresh counter and determining that the current count is greater than a refresh threshold.
摘要翻译：实施例涉及高性能高速缓存架构中的嵌入式动态随机存取存储器（eDRAM）刷新率。一个方面包括接收多个第一信号。经由刷新请求者的刷新请求以包括包括第一信号的子集的间隔的第一刷新率被发送到高速缓冲存储器。第一个刷新率对应于最大刷新率。基于接收到第二信号，刷新计数器被复位。刷新计数器在接收到多个刷新请求之后递增。基于接收到第三信号，从刷新计数器向刷新请求者发送当前计数。刷新请求以小于第一刷新率的第二刷新率发送。基于从刷新计数器接收当前计数并确定当前计数大于刷新阈值来发送刷新请求。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式