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1. 发明申请

US20090006693A1 Apparatus and Method for Fairness Arbitration for a Shared Pipeline in a Large SMP Computer System 有权
标题翻译：大型SMP计算机系统共享管道公平仲裁的装置与方法
公开(公告)号：US20090006693A1
公开(公告)日：2009-01-01
申请号：US11768934
申请日：2007-06-27
申请人： Deanna P. Dunn , Christine C. Jones , Arthur J. O'Neill , Vesselina K. Papazova , Robert J. Sonnelitter, III , Craig R. Walters
发明人： Deanna P. Dunn , Christine C. Jones , Arthur J. O'Neill , Vesselina K. Papazova , Robert J. Sonnelitter, III , Craig R. Walters
IPC分类号： G06F13/14
CPC分类号： G06F13/14 , G06F9/50 , G06F2209/5021 , Y02D10/14 , Y02D10/22
摘要： A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.
摘要翻译：通过共享流水线访问计算机系统资源的等级优先仲裁的修改，通过允许较高排名的请求仅在较低等级的请求者之前访问共享资源，提供更公平的仲裁。如果多个请求同时处于活动状态，则排名优先级将首先选择最高优先级的活动请求并授予对资源的访问权限。它还将设置一个“阻塞锁定”，以防止更高优先级的请求重新获得对资源的访问，直到其余的优先级较低的主动请求者有机会访问该资源。

2. 发明申请

US20110258394A1 MERGING DATA IN AN L2 CACHE MEMORY 有权
标题翻译：兼容L2缓存中的数据
公开(公告)号：US20110258394A1
公开(公告)日：2011-10-20
申请号：US13173840
申请日：2011-06-30
申请人： Deanna P. Dunn , Robert J. Sonnelitter, III , Gary E. Strait
发明人： Deanna P. Dunn , Robert J. Sonnelitter, III , Gary E. Strait
IPC分类号： G06F12/08
CPC分类号： G06F13/28 , G06F12/0866
摘要： A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining that the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data.
摘要翻译：一种用于合并数据的方法，包括接收来自输入/输出设备的请求以合并数据，其中所述数据的合并包括所述数据的操作，确定所述数据存在于与所述数据本地通信的本地高速缓冲存储器中输入/输出设备，如果数据不存在于本地高速缓冲存储器中，则从远程高速缓冲存储器或主存储器将数据提取到本地高速缓冲存储器，根据请求合并数据以获得合并数据，并存储合并的数据在本地高速缓存中，其中在不使用控制流中的存储器控制器或合并数据的数据流的情况下执行数据的合并。

3. 发明授权

US08250305B2 Method, system and computer program product for data buffers partitioned from a cache array 有权
标题翻译：从缓存阵列分区的数据缓冲区的方法，系统和计算机程序产品
公开(公告)号：US08250305B2
公开(公告)日：2012-08-21
申请号：US12051244
申请日：2008-03-19
申请人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
发明人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/126 , G06F2212/2515
摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.
摘要翻译：从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态，响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

4. 发明申请

US20090240891A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DATA BUFFERS PARTITIONED FROM A CACHE ARRAY 有权
标题翻译：方法，系统和计算机程序产品用于从缓存区域分配的数据缓冲区
公开(公告)号：US20090240891A1
公开(公告)日：2009-09-24
申请号：US12051244
申请日：2008-03-19
申请人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
发明人： Gary E. Strait , Deanna P. Dunn , Michael F. Fee , Pak-kin Mak , Robert J. Sonnelitter, III
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F2212/2515
摘要： Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line.
摘要翻译：从缓存阵列分区的数据缓冲区的系统，方法和计算机程序产品。示例性实施例包括处理器中的方法并且用于提供从高速缓存阵列分区的数据缓冲器，该方法包括将与处理器相关联的高速缓存目录清除到初始状态，从由服务处理器预加载的控制寄存器获得所选择的目录状态，响应于包括所需缓存状态的控制寄存器，发送具有地址和数据的加载命令，将高速缓存行和高速缓存行目录条目加载到高速缓存中并将指定的数据存储在相应的高速缓存行中。

5. 发明申请

US20090216915A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MERGING DATA 有权
标题翻译：用于合并数据的方法，系统和计算机程序产品
公开(公告)号：US20090216915A1
公开(公告)日：2009-08-27
申请号：US12036322
申请日：2008-02-25
申请人： Deanna P. Dunn , Robert J. Sonnelitter, III , Gary E. Strait
发明人： Deanna P. Dunn , Robert J. Sonnelitter, III , Gary E. Strait
IPC分类号： G06F13/28 , G06F12/08
CPC分类号： G06F13/28 , G06F12/0866
摘要： A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data. A corresponding system and computer program product.
摘要翻译：一种用于合并数据的方法，包括接收来自输入/输出设备的请求以合并数据，其中所述数据的合并包括对所述数据的操纵，确定所述数据是否存在于与所述数据本地通信的本地高速缓冲存储器中输入/输出设备，如果数据不存在于本地高速缓冲存储器中，则从远程高速缓冲存储器或主存储器将数据提取到本地高速缓冲存储器，根据请求合并数据以获得合并数据，并存储合并的数据在本地高速缓存中，其中在不使用控制流中的存储器控制器或合并数据的数据流的情况下执行数据的合并。相应的系统和计算机程序产品。

6. 发明授权

US08006039B2 Method, system, and computer program product for merging data 有权
标题翻译：用于合并数据的方法，系统和计算机程序产品
公开(公告)号：US08006039B2
公开(公告)日：2011-08-23
申请号：US12036322
申请日：2008-02-25
申请人： Deanna P. Dunn , Robert J. Sonnelitter, III , Gary E. Strait
发明人： Deanna P. Dunn , Robert J. Sonnelitter, III , Gary E. Strait
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F12/0866
摘要： A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data. A corresponding system and computer program product.
摘要翻译：一种用于合并数据的方法，包括接收来自输入/输出设备的请求以合并数据，其中所述数据的合并包括对所述数据的操纵，确定所述数据是否存在于与所述数据本地通信的本地高速缓冲存储器中输入/输出设备，如果数据不存在于本地高速缓冲存储器中，则从远程高速缓冲存储器或主存储器将数据提取到本地高速缓冲存储器，根据请求合并数据以获得合并数据，并存储合并的数据在本地高速缓存中，其中在不使用控制流中的存储器控制器或合并数据的数据流的情况下执行数据的合并。相应的系统和计算机程序产品。

7. 发明授权

US07779189B2 Method, system, and computer program product for pipeline arbitration 失效
标题翻译：管道仲裁的方法，系统和计算机程序产品
公开(公告)号：US07779189B2
公开(公告)日：2010-08-17
申请号：US12035249
申请日：2008-02-21
申请人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
发明人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
IPC分类号： G06F13/36 , G06F12/00 , G06F13/00 , H03M13/00
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译：一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。相应的系统和计算机程序产品。

8. 发明申请

US20090216933A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PIPELINE ARBITRATION 失效
标题翻译：用于管道仲裁的方法，系统和计算机程序产品
公开(公告)号：US20090216933A1
公开(公告)日：2009-08-27
申请号：US12035249
申请日：2008-02-21
申请人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
发明人： Deanna P. Dunn , Garrett M. Drapala , Michael F. Fee , Pak-kin Mak , Craig R. Walters
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译：一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。相应的系统和计算机程序产品。

9. 发明申请

US20090070498A1 Dynamic Data Transfer Control Method and Apparatus for Shared SMP Computer Systems 有权
标题翻译：用于共享SMP计算机系统的动态数据传输控制方法和装置
公开(公告)号：US20090070498A1
公开(公告)日：2009-03-12
申请号：US11853881
申请日：2007-09-12
申请人： Garrett M. Drapala , Deanna P. Dunn , Michael Fee
发明人： Garrett M. Drapala , Deanna P. Dunn , Michael Fee
IPC分类号： G06F3/00
CPC分类号： G06F13/4059 , G06F12/0859
摘要： As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed transfer, the system dynamically time shift or slows down the read rate out of the interleave buffer to half speed, and utilizes the free half of the bandwidth. This dynamic “zippering” or time shifting of data prevents a pipe pass from being rejected because the whole data bus is unavailable.
摘要翻译：由于对计算机系统数据总线的性能关键（高速或全速）请求沿中央管线行进，系统检测接口数据总线当前是否为空或正在进行半速传输。如果存在持续的低速传输，则系统动态地将交织缓冲器中的读取速率移动或减慢到一半速度，并且利用空闲的一半带宽。由于数据总线不可用，这种动态的“拉链”或数据的时间偏移可防止管道传递被拒绝。

10. 发明授权

US07574548B2 Dynamic data transfer control method and apparatus for shared SMP computer systems 有权
标题翻译：用于共享SMP计算机系统的动态数据传输控制方法和装置
公开(公告)号：US07574548B2
公开(公告)日：2009-08-11
申请号：US11853881
申请日：2007-09-12
申请人： Garrett M. Drapala , Deanna P. Dunn , Michael Fee
发明人： Garrett M. Drapala , Deanna P. Dunn , Michael Fee
IPC分类号： G06F13/14 , G06F13/42
CPC分类号： G06F13/4059 , G06F12/0859
摘要： As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed transfer, the system dynamically time shift or slows down the read rate out of the interleave buffer to half speed, and utilizes the free half of the bandwidth. This dynamic “zippering” or time shifting of data prevents a pipe pass from being rejected because the whole data bus is unavailable.
摘要翻译：由于对计算机系统数据总线的性能关键（高速或全速）请求沿中央管线行进，系统检测接口数据总线当前是否为空或正在进行半速传输。如果存在持续的低速传输，则系统动态地将交织缓冲器中的读取速率移动或减慢到一半速度，并且利用空闲的一半带宽。由于数据总线不可用，这种动态的“拉链”或数据的时间偏移可防止管道传递被拒绝。

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