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1. 发明授权

US06501313B2 Dynamic duty cycle adjuster 有权
公开(公告)号：US06501313B2
公开(公告)日：2002-12-31
申请号：US09749335
申请日：2000-12-27
申请人： David William Boerstler , Daniel Mark Dreps , Byron Lee Krauter , Hung Cai Ngo
发明人： David William Boerstler , Daniel Mark Dreps , Byron Lee Krauter , Hung Cai Ngo
IPC分类号： H03K3017
CPC分类号： H03K5/1565
摘要： A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer. Alternatively, the invention may be implemented in an analog fashion, such as by applying an analog signal to the body contact, wherein the analog signal is generated using an asymmetric charge-pump and filter connected to the clock signal.

2. 发明授权

US06566921B1 Apparatus and method for high resolution frequency adjustment in a multistage frequency synthesizer 失效
标题翻译：用于多级频率合成器中高分辨率频率调整的装置和方法
公开(公告)号：US06566921B1
公开(公告)日：2003-05-20
申请号：US09631718
申请日：2000-08-03
申请人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
发明人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
IPC分类号： H03L706
CPC分类号： H03L7/23
摘要： An apparatus and a method for making high resolution frequency adjustments in a multistage frequency synthesizer. The initial stage of the frequency synthesizer is a conventional phase lock loop connected to a dynamically variable frequency divider. There are one or more intermediate stages that consist of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to a dynamically variable frequency divider. The final stage consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to another fixed frequency divider. By varying the constant of division in the variable frequency dividers in the circuit, fine frequency adjustments can be made very rapidly. The precision of the adjustments depends on the relative values of the frequency dividers and the number of intermediate stages in the system.
摘要翻译：一种用于在多级频率合成器中进行高分辨率频率调整的装置和方法。频率合成器的初始阶段是连接到动态可变分频器的常规锁相环。存在一个或多个中间级，其包括通过固定分频器反馈并连接到动态可变分频器的锁相环的前部。最后一个阶段包括通过固定分频器反馈并连接到另一个固定分频器的锁相环的前向部分。通过改变电路中可变分频器的分频常数，可以非常快速地进行微调频率调整。调整精度取决于分频器的相对值和系统中的中间级数。

3. 发明授权

US06522207B1 Apparatus and method for dynamic frequency adjustment in a frequency synthesizer 有权
标题翻译：频率合成器中动态频率调整的装置和方法
公开(公告)号：US06522207B1
公开(公告)日：2003-02-18
申请号：US09631720
申请日：2000-08-03
申请人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
发明人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
IPC分类号： H03L700
CPC分类号： H03L7/23 , G06F7/68 , H03L7/183
摘要： An apparatus and a method for making small frequency adjustments in a frequency synthesizer. The frequency synthesizer consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and the output of the forward portion of the phase locked loop connected to a dynamically variable frequency divider. By changing the constant of division in the variable frequency divider, the output of the frequency divider can be rapidly changed in small increments. The dynamically variable frequency divider is key to this design. This digital circuit stores the current divisor value and has an input for a new divisor value. When a signal is sent to switch to the new divisor value, the circuit uses an incrementer and associated logic to rapidly change to the new constant of division.
摘要翻译：一种用于在频率合成器中进行小频率调整的装置和方法。频率合成器包括通过固定分频器的反馈的锁相环的前向部分和连接到动态可变分频器的锁相环的前部的输出。通过改变可变分频器中的分频常数，分频器的输出可以以小的增量快速变化。动态可变分频器是本设计的关键。该数字电路存储当前除数值，并具有新的除数值的输入。当发送信号以切换到新的除数值时，电路使用增量器和相关联的逻辑来快速变化到新的除法常数。

4. 发明授权

US06529084B1 Interleaved feedforward VCO and PLL 有权
标题翻译：交错前馈VCO和PLL
公开(公告)号：US06529084B1
公开(公告)日：2003-03-04
申请号：US09974986
申请日：2001-10-11
申请人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03B524
CPC分类号： H03L7/0998 , H03K3/0315 , H03L7/0891 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) and phase-locked loop (PLL) topologies that allow for low-voltage, high frequency, low-jitter operation are disclosed. The conventional PLL design is modified so as to bifurcate the error signal into AC and DC components. A VCO accepting AC- and DC-component control inputs adjusts its output frequency in accordance with both inputs.
摘要翻译：公开了一种允许低电压，高频，低抖动操作的压控振荡器（VCO）和锁相环（PLL）拓扑。传统的PLL设计被修改为将误差信号分成AC和DC分量。接受AC和DC分量控制输入的VCO根据两个输入调节其输出频率。

5. 发明授权

US06335650B1 Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages 有权
标题翻译：用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置
公开(公告)号：US06335650B1
公开(公告)日：2002-01-01
申请号：US09670829
申请日：2000-09-28
申请人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K19/00384 , H03K19/018585 , H03K2005/0013
摘要： A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.
摘要翻译：公开了一种用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置。电压电平检测器和延迟装置耦合到能够在多个电源电压下工作的集成电路的关键定时电路。电压电平检测器检测集成电路正在工作的电源电压。当集成电路的工作电源电压从第一电压电平变化到第二电压电平时，电压电平检测器向延迟装置和当前增强电路发送信号，使得延迟装置和电流增强电路可以自动修改来自关键定时电路的输出信号的切换时间的延迟。

6. 发明授权

US06763474B1 System for synchronizing nodes in a heterogeneous computer system by using multistage frequency synthesizer to dynamically adjust clock frequency of the nodes 失效
标题翻译：通过使用多级频率合成器来动态调整节点的时钟频率来同步异构计算机系统中的节点的系统
公开(公告)号：US06763474B1
公开(公告)日：2004-07-13
申请号：US09631712
申请日：2000-08-03
申请人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
发明人： David William Boerstler , Mark Edward Dean , Hung Cai Ngo , Andrew Christian Zimmerman
IPC分类号： G06P112
CPC分类号： H03L7/23
摘要： An apparatus and a method for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. Time stamps, which are critically important, are attached to transaction requests. Time stamps are based on a “time of day” value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates may be lost. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.
摘要翻译：用于节点同步的装置和方法，其可以用于系统中的节点不共享公共系统时钟的异构计算机系统中。重要的时间戳附加在交易请求上。时间戳基于“时间”值，其可以简单地是由系统时钟增加的寄存器。由于每个节点都有自己的系统时钟，这些时钟的频率可能会偏移，这会导致时间戳值的变化。如果值漂移太远，数据更新可能会丢失。能够将高分辨率和快速频率调节的频率合成器连接到系统时钟。当检测到主从时间之间的相位偏移时，可以将频率合成器输出改变少量以使两个信号回到相位。

7. 发明授权

US07995418B2 Method and computer program for controlling a storage device having per-element selectable power supply voltages 有权
标题翻译：用于控制具有每元件可选电源电压的存储装置的方法和计算机程序
公开(公告)号：US07995418B2
公开(公告)日：2011-08-09
申请号：US12399551
申请日：2009-03-06
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： A method and computer program product for controlling a storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：用于使用每元素可选择的电源电压来控制存储设备的方法和计算机程序产品在保持特定性能水平的同时在存储设备中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

8. 发明授权

US07551508B2 Energy efficient storage device using per-element selectable power supply voltages 失效
标题翻译：使用每元件可选电源电压的节能存储设备
公开(公告)号：US07551508B2
公开(公告)日：2009-06-23
申请号：US11941168
申请日：2007-11-16
申请人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
发明人： Rajiv V. Joshi , Jente B Kuang , Rouwaida N. Kanj , Sani R. Nassif , Hung Cai Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.
摘要翻译：使用每元件可选择的电源电压的节能存储装置在保持特定的性能水平的同时在存储装置中提供节能。存储设备被划分成多个元素，其可以是子阵列，行，列或单独的存储单元。每个元件具有相应的虚拟电源轨，其具有可选择的电源电压。提供给用于元件的虚拟电源轨的电源电压被设置为最小电源电压，除非元件满足性能要求需要更高的电源电压。可以在每个元件内提供控制单元，其提供选择提供给相应的虚拟电源轨的电源电压的控制信号。可以通过熔丝或掩模设置单元的状态，或者可以在存储设备初始化时将值加载到控制单元中。

9. 发明授权

US07545690B2 Method for evaluating memory cell performance 失效
标题翻译：评估存储单元性能的方法
公开(公告)号：US07545690B2
公开(公告)日：2009-06-09
申请号：US11741187
申请日：2007-04-27
申请人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译：用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作。该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。弱写入条件和/或弱写入条件可以通过选择性加载来测量。

10. 发明申请

US20080273403A1 STORAGE CELL DESIGN EVALUATION CIRCUIT INCLUDING A WORDLINE TIMING AND CELL ACCESS DETECTION CIRCUIT 失效
标题翻译：存储单元设计评估电路，包括WORDLINE时序和细胞检测电路
公开(公告)号：US20080273403A1
公开(公告)日：2008-11-06
申请号：US12125011
申请日：2008-05-21
申请人： Sebastian Ehrenreich , Jente B. Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B. Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A storage cell design evaluation circuit including a wordline timing and cell access detection circuit provides accurate information about state changes in static storage cells. A storage cell test row includes the access detection circuit, which provides the same loading during an access operation as the other cells in the array. The access detection circuit provides an output that may be probed without affecting the timing, read stability or writeability of the cell. The test row can test the clock and/or address timing of the row and may include a separate power supply rail for the row wordline driver, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译：包括字线定时和单元访问检测电路的存储单元设计评估电路提供关于静态存储单元中的状态变化的精确信息。存储单元测试行包括访问检测电路，其在与阵列中的其他单元的访问操作期间提供相同的负载。访问检测电路提供可以探测的输出，而不影响单元的定时，读取稳定性或可写性。测试行可以测试行的时钟和/或地址时序，并且可以包括用于行字线驱动器的单独的电源轨，从而可以确定访问时序，读取稳定性和可写入性与字线强度/访问电压的变化。多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。

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