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    • 3. 发明申请
    • Color management system and method for a visual display apparatus
    • 用于视觉显示装置的颜色管理系统和方法
    • US20080048956A1
    • 2008-02-28
    • US11507844
    • 2006-08-22
    • David W. RekietaNguyen HoGetzel Gonzalez Garcia
    • David W. RekietaNguyen HoGetzel Gonzalez Garcia
    • G09G3/34
    • G09G3/346G09G2320/0242G09G2320/0693G09G2360/145
    • According to one embodiment of the present invention, a color management system for a visual display apparatus comprises a light source operable to produce a light beam having at least one color component, wherein at least one color component has a plurality of visual characteristics defining the quality of the color component. The system also has a light modulator operable to modulate the light beam into the image for displaying upon a display, an illumination sensor operable to monitor at least one visual characteristic of the at least one color component, and a feedback controller that is operable to modify the relative intensity of at least one color component due to deviation of the at least visual characteristic of at least one color component from at least one visual characteristic value during operation of the system.
    • 根据本发明的一个实施例,用于视觉显示设备的颜色管理系统包括可操作以产生具有至少一个颜色分量的光束的光源,其中至少一个颜色分量具有限定质量的多个视觉特性 的颜色成分。 该系统还具有光调制器,其可操作以将光束调制成图像以在显示器上显示,可操作以监视至少一个颜色分量的至少一个视觉特征的照明传感器和可操作以修改的反馈控制器 由于至少一种颜色分量的至少视觉特征与系统操作期间的至少一个视觉特征值的偏差,至少一种颜色分量的相对强度。
    • 4. 发明授权
    • Circuits, systems, and methods for efficient wake up of peripheral component interconnect controller
    • 外围组件互连控制器高效唤醒的电路,系统和方法
    • US06473810B1
    • 2002-10-29
    • US09407471
    • 1999-09-28
    • Krunali T. PatelMark A. BeadleDavid W. Rekieta
    • Krunali T. PatelMark A. BeadleDavid W. Rekieta
    • G06F300
    • G06F1/3203G06F1/3253Y02D10/151
    • A controller (203) for coupling between a computer bus (20) and one or more units (221, 222) compatible with the bus. The controller comprises a first input (28) for receiving a first reset signal issued from the computer bus, and a second input (30) for receiving a second reset signal. The controller further comprises circuitry (26) for storing a first set of information which will be cleared in response to assertion of the first reset signal. Lastly, the controller comprises circuitry (24) for storing a second set of information which will not be cleared in response to assertion of the first reset signal but which will be cleared in response to assertion of the second reset signal. In a described embodiment, the bus is a PCI bus, the first reset signal is a PCI Reset signal, and the second reset signal is an initialization signal.
    • 一种用于在计算机总线(20)与与总线兼容的一个或多个单元(221,222)之间耦合的控制器(203)。 控制器包括用于接收从计算机总线发出的第一复位信号的第一输入端(28)和用于接收第二复位信号的第二输入端(30)。 控制器还包括用于存储将响应于第一复位信号的断言而被清除的第一组信息的电路(26)。 最后,控制器包括用于存储第二组信息的电路(24),该第二组信息将不响应于第一复位信号的断言而被清除,而响应于第二复位信号的断言将被清除。 在所描述的实施例中,总线是PCI总线,第一复位信号是PCI复位信号,第二复位信号是初始化信号。
    • 6. 发明授权
    • Dynamic device power management
    • 动态设备电源管理
    • US6151681A
    • 2000-11-21
    • US102245
    • 1998-06-22
    • Philip A. RodenPatrick C. NeilDavid W. Rekieta
    • Philip A. RodenPatrick C. NeilDavid W. Rekieta
    • G06F1/32G06F1/12
    • G06F1/3237G06F1/3203G06F1/3287Y02B60/1221Y02B60/1282
    • A power management method and system which includes providing a system having a plurality of clock operated circuits, each clock operated circuit being operable in response to the receipt of clock signals. A first subplurality of the clock operated circuits receives an uninterrupted stream of clock signals and thereby is uninterruptably operable and a second plurality of the clock operated circuits receives a normally off interruptable stream of clock signals and is normally inoperable. The system is sampled for the presence of data signals being input thereto. The clock signals are sent to the second plurality of circuits in response to the sampling the presence of data signals being input to the system to cause the second plurality of circuits to be operable. The data signals are transmitted to the second plurality of circuits after a time delay equal to or greater than the expired time from the sampling to the sending. The system can have a plurality of input/output terminals with the sampling comprising being at each of the input/output terminals. The system includes a clock for providing the clock signals and a decode logic for sampling at one of the input/output terminals and an arbiter circuit for sampling at the other input/output terminal.
    • 一种电源管理方法和系统,其包括提供具有多个时钟操作电路的系统,每个时钟操作电路可响应于时钟信号的接收来操作。 时钟操作电路的第一子部分接收不间断的时钟信号流,从而不间断地操作,并且第二多个时钟操作电路接收正常关断的可中断时钟信号流,并且通常是不可操作的。 对输入的数据信号的存在进行采样。 所述时钟信号响应于对所述系统输入的数据信号的存在进行采样而被发送到所述第二多个电路,以使所述第二多个电路可操作。 在等于或大于从采样到发送的到期时间的时间延迟之后,数据信号被发送到第二多个电路。 该系统可以具有多个输入/输出端子,其中采样包括在每个输入/输出端子处。 该系统包括用于提供时钟信号的时钟和用于在输入/输出端子之一处采样的解码逻辑和用于在另一个输入/输出端子处进行采样的仲裁器电路。