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1. 发明授权

US08095739B2 Barriers processing in a multiprocessor system having a weakly ordered storage architecture without broadcast of a synchronizing operation 失效
标题翻译：在具有弱排序存储体系结构的多处理器系统中进行障碍处理，而无需广播同步操作
公开(公告)号：US08095739B2
公开(公告)日：2012-01-10
申请号：US12422698
申请日：2009-04-13
申请人： David W. Cummings , Guy L. Guthrie , Harmony L. Helterhoff , Derek E. Williams
发明人： David W. Cummings , Guy L. Guthrie , Harmony L. Helterhoff , Derek E. Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F12/0815 , G06F12/0862 , G06F12/126
摘要： A data processing system employing a weakly ordered storage architecture includes first and second sets of processing units coupled to each other and data storage by an interconnect fabric. Each processing unit has a processor core having an associated cache hierarchy including at least a level one, level two and level three cache memories. A request to perform an update to a portion of a first image of memory contained in the level three cache memory of a first processing unit while at last one kill-type command is pending at the first processing unit, the cache hierarchy of the first processing unit permitting the update to be exposed to any first processor core only after the at least one kill-type command is complete.
摘要翻译：采用弱有序存储架构的数据处理系统包括彼此耦合的第一和第二组处理单元以及互连结构的数据存储。每个处理单元具有处理器核心，其具有包括至少一级，二级和三级高速缓冲存储器的相关联的高速缓存层级。在最后一个杀死型命令时，对包含在第一处理单元的三级高速缓冲存储器中的存储器的第一图像的一部分进行更新的请求在第一处理单元处于等待状态，第一处理的高速缓存层级单元允许仅在至少一个杀死型命令完成之后将更新暴露给任何第一处理器核。

2. 发明申请

US20100262786A1 Barriers Processing in a Multiprocessor System Having a Weakly Ordered Storage Architecture Without Broadcast of a Synchronizing Operation 失效
标题翻译：具有弱序列存储架构的多处理器系统中的障碍处理，无需广播同步操作
公开(公告)号：US20100262786A1
公开(公告)日：2010-10-14
申请号：US12422698
申请日：2009-04-13
申请人： David W. Cummings , Guy L. Guthrie , Harmony L. Helterhoff , Derek E. Williams
发明人： David W. Cummings , Guy L. Guthrie , Harmony L. Helterhoff , Derek E. Williams
IPC分类号： G06F12/08 , G06F9/46
CPC分类号： G06F12/0897 , G06F12/0815 , G06F12/0862 , G06F12/126
摘要： A data processing system employing a weakly ordered storage architecture includes first and second sets of processing units coupled to each other and data storage by an interconnect fabric. Each processing unit has a processor core having an associated cache hierarchy including at least a level one, level two and level three cache memories. In response to a request to perform an update to a portion of a first image of memory contained in the level three cache memory of a first processing unit while at last one kill-type command is pending at the first processing unit, the cache hierarchy of the first processing unit permitting the update to be exposed to any first processor core only after the at least one kill-type command is complete.
摘要翻译：采用弱有序存储架构的数据处理系统包括彼此耦合的第一和第二组处理单元以及互连结构的数据存储。每个处理单元具有处理器核心，其具有包括至少一级，二级和三级高速缓冲存储器的相关联的高速缓存层级。响应于对包含在第一处理单元的三级高速缓冲存储器中的存储器的第一图像的一部分执行更新的请求，而最后一个杀死型命令在第一处理单元处于等待状态，则高速缓存层级所述第一处理单元仅在所述至少一个杀死型命令完成之后允许所述更新暴露于任何第一处理器核心。

3. 发明申请

US20100268884A1 Updating Partial Cache Lines in a Data Processing System 有权
标题翻译：更新数据处理系统中的部分缓存行
公开(公告)号：US20100268884A1
公开(公告)日：2010-10-21
申请号：US12424434
申请日：2009-04-15
申请人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0822 , G06F12/0897 , G06F2212/507
摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
摘要翻译：用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。处理单元还包括耦合到并支持处理器核的多级高速缓存层级。多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送到至少一个上级高速缓冲存储器以服务存储器访问请求。至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。

4. 发明授权

US08117390B2 Updating partial cache lines in a data processing system 有权
标题翻译：更新数据处理系统中的部分缓存行
公开(公告)号：US08117390B2
公开(公告)日：2012-02-14
申请号：US12424434
申请日：2009-04-15
申请人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： David W. Cummings , Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F13/00
CPC分类号： G06F12/0822 , G06F12/0897 , G06F2212/507
摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.
摘要翻译：用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。处理单元还包括耦合到并支持处理器核的多级高速缓存层级。多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送至至少一个上级高速缓冲存储器来服务存储器访问请求。至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。

5. 发明授权

US08312220B2 Mode-based castout destination selection 失效
标题翻译：基于模式的castout目的地选择
公开(公告)号：US08312220B2
公开(公告)日：2012-11-13
申请号：US12420933
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Phillip G. Williams , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Phillip G. Williams , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/12
摘要： In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing.
摘要翻译：响应于多个处理单元中的第一处理单元的数据请求，第一处理单元从第一处理单元的较低级高速缓存中选择要丢弃的牺牲高速缓存行，并且确定是否设置了模式。如果不是，则第一处理单元在互连结构上发出识别受害者高速缓存行的LCO命令，并指示较低级别的高速缓存是预期的目的地。如果模式被设置，则第一处理单元发出具有替代预定目的地的停顿命令。响应于指示LCO命令成功的LCO命令的一致性响应，第一处理单元从其较低级高速缓存中去除受害者高速缓存行，并且将受害者高速缓存行保持在数据处理系统的其他地方。该模式可以设置为抑制系统内存的丢弃，例如进行测试。

6. 发明授权

US08291259B2 Delete of cache line with correctable error 失效
标题翻译：删除具有可纠正错误的缓存行
公开(公告)号：US08291259B2
公开(公告)日：2012-10-16
申请号：US12424412
申请日：2009-04-15
申请人： Guy L. Guthrie , Harmony L. Helterhoff , Kevin F. Reick , Phillip G. Williams
发明人： Guy L. Guthrie , Harmony L. Helterhoff , Kevin F. Reick , Phillip G. Williams
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/073 , G06F11/076 , G06F11/1064 , G06F12/0802 , G06F12/126
摘要： A processing unit includes a processor core and a cache memory coupled to the processor core. The cache memory includes a data array, a directory of the data array, error detection logic that sequentially detects a first, second and third correctable errors in the data array of the cache memory and provides indications of detection of the first, second and third correctable errors, and control circuitry that, responsive to the indication of the third correctable error and an indication that the first and second correctable errors occurred at too high a frequency, marks an entry of the data array containing a cache line having the third correctable error as deleted in the directory of the cache memory regardless of which entry of the data array contains a cache line having the second correctable error.
摘要翻译：处理单元包括处理器核心和耦合到处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的目录，错误检测逻辑，其顺序地检测高速缓冲存储器的数据阵列中的第一，第二和第三可校正错误，并提供第一，第二和第三可校正的检测指示错误和控制电路，其响应于第三可校正错误的指示和第一和第二可校正错误在太高频率处发生的指示，将包含具有第三可校正错误的高速缓存行的数据阵列的条目标记为在高速缓冲存储器的目录中被删除，而不管数据阵列的哪个条目包含具有第二可校正错误的高速缓存行。

7. 发明申请

US20100268984A1 Delete Of Cache Line With Correctable Error 失效
标题翻译：删除缓存线与可纠正的错误
公开(公告)号：US20100268984A1
公开(公告)日：2010-10-21
申请号：US12424412
申请日：2009-04-15
申请人： Guy L. Guthrie , Harmony L. Helterhoff , Kevin F. Reick , Phillip G. Williams
发明人： Guy L. Guthrie , Harmony L. Helterhoff , Kevin F. Reick , Phillip G. Williams
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/073 , G06F11/076 , G06F11/1064 , G06F12/0802 , G06F12/126
摘要： A processing unit includes a processor core and a cache memory coupled to the processor core. The cache memory includes a data array, a directory of the data array, error detection logic that sequentially detects a first, second and third correctable errors in the data array of the cache memory and provides indications of detection of the first, second and third correctable errors, and control circuitry that, responsive to the indication of the third correctable error and an indication that the first and second correctable errors occurred at too high a frequency, marks an entry of the data array containing a cache line having the third correctable error as deleted in the directory of the cache memory regardless of which entry of the data array contains a cache line having the second correctable error.
摘要翻译：处理单元包括处理器核心和耦合到处理器核心的高速缓存存储器。高速缓冲存储器包括数据阵列，数据阵列的目录，错误检测逻辑，其顺序地检测高速缓冲存储器的数据阵列中的第一，第二和第三可校正错误，并提供第一，第二和第三可校正的检测指示错误和控制电路，其响应于第三可校正错误的指示和第一和第二可校正错误在太高频率处发生的指示，将包含具有第三可校正错误的高速缓存行的数据阵列的条目标记为在高速缓冲存储器的目录中被删除，而不管数据阵列的哪个条目包含具有第二可校正错误的高速缓存行。

8. 发明申请

US20100262778A1 Empirically Based Dynamic Control of Transmission of Victim Cache Lateral Castouts 有权
标题翻译：基于经验的动态控制受害者缓存横向铸件传动
公开(公告)号：US20100262778A1
公开(公告)日：2010-10-14
申请号：US12421180
申请日：2009-04-09
申请人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： Robert A. Cargnoni , Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0862 , G06F12/127 , G06F2212/6026
摘要： In response to a data request, a victim cache line is selected for castout from a lower level cache, and a target lower level cache of one of the plurality of processing units is selected. A determination is made whether the selected target lower level cache has provided more than a threshold number of retry responses to lateral castout (LCO) commands of the first lower level cache, and if so, a different target lower level cache is selected. The first processing unit thereafter issues a LCO command on the interconnect fabric. The LCO command identifies the victim cache line to be castout and indicates that the target lower level cache is an intended destination of the victim cache line. In response to a successful coherence response to the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.
摘要翻译：响应于数据请求，选择从较低级别高速缓冲存储器进行丢弃的受害者高速缓存行，并且选择多个处理单元之一的目标下级高速缓存。确定所选择的目标下层高速缓存是否为第一较低级别高速缓存的横向转移（LCO）命令提供了超过阈值数量的重试响应，如果是，则选择不同的目标低级高速缓存。此后，第一处理单元在互连结构上发出LCO命令。 LCO命令标识要丢弃的受害者缓存行，并指示目标下级缓存是受害缓存行的预期目标。响应于对LCO命令的成功的一致性响应，从第一低级缓存中移除受害者高速缓存行并保存在第二较低级缓存中。

9. 发明申请

US20100262783A1 Mode-Based Castout Destination Selection 失效
标题翻译：基于模式的Castout目的地选择
公开(公告)号：US20100262783A1
公开(公告)日：2010-10-14
申请号：US12420933
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
发明人： Guy L. Guthrie , Harmony L. Helterhoff , William J. Starke , Jeffrey A. Stuecheli , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/12
摘要： In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing.
摘要翻译：响应于多个处理单元中的第一处理单元的数据请求，第一处理单元从第一处理单元的较低级高速缓存中选择要丢弃的牺牲高速缓存行，并且确定是否设置了模式。如果不是，则第一处理单元在互连结构上发出识别受害者高速缓存行的LCO命令，并指示较低级别的高速缓存是预期的目的地。如果模式被设置，则第一处理单元发出具有替代预定目的地的停顿命令。响应于指示LCO命令成功的LCO命令的一致性响应，第一处理单元从其较低级高速缓存中去除受害者高速缓存行，并且将受害者高速缓存行保持在数据处理系统的其他地方。该模式可以设置为抑制系统内存的丢弃，例如进行测试。

10. 发明申请

US20100262784A1 Empirically Based Dynamic Control of Acceptance of Victim Cache Lateral Castouts 有权
标题翻译：基于经验的动态控制接受受害者缓存横向铸件
公开(公告)号：US20100262784A1
公开(公告)日：2010-10-14
申请号：US12421017
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , Thomas L. Jeremiah , Alvan W. Ng , William J. Starke , Jeffrey A. Stuecheli , Philip G. Williams
发明人： Guy L. Guthrie , Harmony L. Helterhoff , Thomas L. Jeremiah , Alvan W. Ng , William J. Starke , Jeffrey A. Stuecheli , Philip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/0811 , G06F12/0815 , G06F12/0862
摘要： A second lower level cache receives an LCO command issued by a first lower level cache on an interconnect fabric. The LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line. The second lower level cache determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command. In response to determining not to accept the victim cache line, the second lower level cache provides a coherence response to the LCO command refusing the identified victim cache line. In response to determining to accept the victim cache line, the second lower level cache updates an entry corresponding to the identified victim cache line.
摘要翻译：第二低级缓存接收由互连结构上的第一较低级缓存发出的LCO命令。 LCO命令指示要从第一较低级高速缓存丢弃的受害者高速缓存行的地址，并且指示第二较低级高速缓存是受害者高速缓存行的预期目的地。第二较低级缓存至少部分地基于由LCO命令指示的受害缓存行的地址来确定是否从第一低级缓存接受受害者高速缓存行。响应于确定不接受受害者缓存行，第二较低级缓存为LCO命令提供拒绝所识别的受害者缓存行的一致性响应。响应于确定接受受害者缓存行，第二较低级缓存更新对应于所识别的受害者高速缓存行的条目。

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