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1. 发明授权

US06745357B2 Dynamic logic scan gate method and apparatus 有权
标题翻译：动态逻辑扫描门法和装置
公开(公告)号：US06745357B2
公开(公告)日：2004-06-01
申请号：US09901411
申请日：2001-07-09
申请人： David W. Chrudimsky , Stephen C. Horne , James S. Blomgren , Michael R. Seningen
发明人： David W. Chrudimsky , Stephen C. Horne , James S. Blomgren , Michael R. Seningen
IPC分类号： G01R3128
CPC分类号： H03K19/096
摘要： A method and apparatus for random-access scan of a network 990 of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates (900) driven by multiple overlapping clock signals generated from a clock generation circuit (904) coupled to a clock spine (902). Each clocked precharge logic gate and each scan gate include a logic tree (502) with one or more evaluate nodes, a precharge circuit (32), an evaluate circuit (36), and one or more output buffers (34). Each scan gate further includes a scan circuit (806) that accepts scan control signals (406, 408, 410, 824, and 826) and couples to one or more scan registers (416) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.
摘要翻译：动态逻辑或N-NARY逻辑的网络990的随机存取扫描的方法和装置，其包括顺序时钟的预充电逻辑门和由从时钟发生电路产生的多个重叠时钟信号驱动的一个或多个扫描门（900） 904），其耦合到时钟脊（902）。每个时钟预充电逻辑门和每个扫描门包括具有一个或多个评估节点的逻辑树（502），预充电电路（32），评估电路（36）和一个或多个输出缓冲器（34）。每个扫描门还包括扫描电路（806），其接收扫描控制信号（406,408,410,824和826）并且以类似RAM的架构耦合到一个或多个扫描寄存器（416）。扫描控制信号操作以捕获扫描门的输出缓冲器的状态，并且迫使扫描门的输出缓冲器达到预选的电平。

2. 发明授权

US06911846B1 Method and apparatus for a 1 of N signal 失效
标题翻译： 1个N信号的方法和装置
公开(公告)号：US06911846B1
公开(公告)日：2005-06-28
申请号：US09019278
申请日：1998-02-05
申请人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
发明人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
IPC分类号： G11C8/10 , G11C11/56 , H03K19/003 , H03K19/096
CPC分类号： G11C11/56 , G11C7/1006 , G11C8/10 , H03K19/00346 , H03K19/0963
摘要： The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention comprises a logic tree circuit coupled to a first 1 of N input signal, a second 1 of N input signal, and a 1 of N output signal where the 1 of N signals' reduce the signal's wire to wire effective capacitance. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and one of the wires of the signal is active.
摘要翻译：本发明包括一种用于集成电路（IC）的方法和装置，其使用N个信号中的1个来减少电路的导线以有效电容。本发明包括一个逻辑树电路，其耦合到N个输入信号的第一个1，N个输入信号的第二个1和N个输出信号中的1个，其中N个信号的1个将信号的导线降低到有线电容。本发明的其它实施例包括使用2个信号中的1个，3个信号中的1个，4个信号中的1个，以及信号中的一个和一个有效的8个信号中的1个信号。

3. 发明授权

US6104642A Method and apparatus for 1 of 4 register file design 有权
标题翻译： 1/4寄存器文件设计方法和装置
公开(公告)号：US6104642A
公开(公告)日：2000-08-15
申请号：US207806
申请日：1998-12-09
申请人： James S. Blomgren , Terence M. Potter , Michael R. Seningen , Stephen C. Horne
发明人： James S. Blomgren , Terence M. Potter , Michael R. Seningen , Stephen C. Horne
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21 , G11C7/00
CPC分类号： G06F7/5443 , G06F1/08 , G06F17/5045 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/49 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215 , G06F2207/3824 , G06F7/483 , G06F7/508 , G11C7/1006
摘要： The present invention is a method and apparatus for a register cell that is configured to store information. The cell includes a multiplexer that is configurable to select various inputs when the multiplexer is in various states. The multiplexer is configurable to select a first input when the multiplexer is in a first state, and to select a second input when the multiplexer is in a second state. The multiplexer is further configured to provide storage data, the first input being configured to receive data from outside the cell. An output element, such as a second multiplexer, is configured to receive a word enable. The output of the first multiplexer is delayed in a delay element, and is provided as one of the inputs to the first multiplexer.
摘要翻译：本发明是一种用于存储信息的寄存器单元的方法和装置。该单元包括多路复用器，其可配置为当多路复用器处于不同状态时选择各种输入。多路复用器可配置为当多路复用器处于第一状态时选择第一输入，并且当多路复用器处于第二状态时选择第二输入。复用器还被配置为提供存储数据，第一输入被配置为从单元外部接收数据。诸如第二多路复用器的输出元件被配置为接收字使能。第一多路复用器的输出在延迟元件中延迟，并且被提供为第一多路复用器的输入之一。

4. 发明授权

US06571378B1 Method and apparatus for a N-NARY logic circuit using capacitance isolation 有权
标题翻译：使用电容隔离的N-NARY逻辑电路的方法和装置
公开(公告)号：US06571378B1
公开(公告)日：2003-05-27
申请号：US09587729
申请日：2000-06-05
申请人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
发明人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
IPC分类号： G06F1750
CPC分类号： G11C8/00 , G06F1/08 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215
摘要： A logic device with improved capacitance isolation and a design methodology that reduces parasitic capacitance is disclosed. The logic device includes a virtual ground node, a plurality of input signals that may be individual wires of one or more N-NARY signals, and two or more discharge paths. Each discharge path includes an evaluate node, one or more transistors gated by the input signals, and one or more intermediate nodes, one of which is coupled to the virtual ground node. In one embodiment, the discharge paths are perfectly isolated from each other for every combination of inputs. In another embodiment, intermediate nodes on discharge paths maybe electrically coupled to the evaluation path only at the intermediate node coupled to the virtual ground node.
摘要翻译：公开了具有改善的电容隔离的逻辑器件和减小寄生电容的设计方法。逻辑器件包括虚拟接地节点，可以是一个或多个N-NARY信号的单独线的多个输入信号以及两个或更多个放电路径。每个放电路径包括评估节点，由输入信号选通的一个或多个晶体管，以及一个或多个中间节点，其中一个中间节点耦合到虚拟接地节点。在一个实施例中，对于输入的每个组合，排出路径彼此完全隔离。在另一个实施例中，放电路径上的中间节点可以仅在耦合到虚拟接地节点的中间节点处电耦合到评估路径。

5. 发明授权

US06415405B1 Method and apparatus for scan of synchronized dynamic logic using embedded scan gates 有权
标题翻译：使用嵌入式扫描门扫描同步动态逻辑的方法和装置
公开(公告)号：US06415405B1
公开(公告)日：2002-07-02
申请号：US09468759
申请日：1999-12-21
申请人： Stephen C. Horne , James S. Blomgren , Michael R. Seningen
发明人： Stephen C. Horne , James S. Blomgren , Michael R. Seningen
IPC分类号： G01R3128
CPC分类号： H03K19/096
摘要： A method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates is disclosed. Each clocked precharge logic gate and each scan gate further comprise a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers. Each scan gate further comprises a scan circuit that accepts scan control signals and couples to one or more scan registers in a RAM-like architecture. A scan control circuit generates scan control signals and scan timing signals which operate to capture the state of the output buffers of the scan gate and provide that state to one or more scan registers. Scan control signals and scan timing signals also operate to force the output buffers of the scan gate to a preselected level, which then propagates through the network to create an output state on the next scan gate in the network, which can then be read and compared to an expected output state given the output state of the previous scan gate.
摘要翻译：一种用于动态逻辑或N-Nary逻辑网络的随机存取扫描的方法和装置，其中所述网络包括顺序时钟的预充电逻辑门和一个或多个扫描门。每个时钟预充电逻辑门和每个扫描门还包括具有一个或多个评估节点，预充电电路，评估电路和一个或多个输出缓冲器的逻辑树。每个扫描门还包括扫描电路，该扫描电路接受扫描控制信号并且以类似RAM的架构耦合到一个或多个扫描寄存器。扫描控制电路产生扫描控制信号和扫描定时信号，其操作以捕获扫描门的输出缓冲器的状态，并将该状态提供给一个或多个扫描寄存器。扫描控制信号和扫描定时信号也可以将扫描门的输出缓冲器强制到预选的电平，然后传输通过网络在网络中的下一个扫描门上产生输出状态，然后可以读取和比较到给定前一扫描门的输出状态的预期输出状态。

6. 发明授权

US06252425B1 Method and apparatus for an N-NARY logic circuit 有权
标题翻译：用于N-NARY逻辑电路的方法和装置
公开(公告)号：US06252425B1
公开(公告)日：2001-06-26
申请号：US09458763
申请日：1999-12-10
申请人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M Petro
发明人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M Petro
IPC分类号： H03K19094
CPC分类号： G06F1/08 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215
摘要： The present invention is a method and apparatus for an N-NARY logic circuit that uses N-NARY signals. The present invention includes a shared logic tree circuit that evaluates one or more N-NARY input signals and produces an N-NARY output signal. The present invention additionally includes a first N-NARY input signal coupled to the shared logic tree circuit and a second N-NARY input signal coupled to the shared logic tree circuit. The shared logic circuit evaluates the first second and second N-NARY input signal and produces an N-NARY output signal coupled, which additionally couples to the shared logic tree circuit. The present invention uses signals that include 1 of 2 N-NARY signals, 1 of 3 N-NARY signals, 1 of 4 N-NARY signals, 1 of 8 N-NARY signals, and the general 1 of N N-NARY signals. The present invention evaluates any given function that includes the AND/NAND, OR/NOR, or XOR/Equivalence functions.
摘要翻译：本发明是一种使用N-NARY信号的N-NARY逻辑电路的方法和装置。本发明包括共享逻辑树电路，其评估一个或多个N-NARY输入信号并产生N-NARY个输出信号。本发明还包括耦合到共享逻辑树电路的第一N-NARY输入信号和耦合到共享逻辑树电路的第二N-NARY输入信号。共享逻辑电路评估第一第二和第二N-NARY输入信号并产生耦合的N-NARY输出信号，其另外耦合到共享逻辑树电路。本发明使用包括2个N-NARY信号中的1个，3个N-NARY信号中的1个，4个N-NARY信号中的1个，8个N-NARY个信号中的1个，以及N N-NARY个信号的通用信号1的信号。本发明评估包括AND / NAND，OR / NOR或异或/等效函数的任何给定函数。

7. 发明授权

US06118716A Method and apparatus for an address triggered RAM circuit 有权
标题翻译：地址触发RAM电路的方法和装置
公开(公告)号：US06118716A
公开(公告)日：2000-09-12
申请号：US150389
申请日：1998-09-09
申请人： Stephen C. Horne , Michael R. Seningen , James S. Blomgren
发明人： Stephen C. Horne , Michael R. Seningen , James S. Blomgren
IPC分类号： G06F1/08 , G06F17/50 , G11C7/02 , G11C8/10 , G11C8/18 , G11C11/418 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/096
CPC分类号： G06F17/5045 , G06F1/08 , G11C11/418 , G11C11/56 , G11C19/00 , G11C8/10 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0963 , G11C7/1006
摘要： A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-nary, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-nary, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-nary) 1-of-N logic gate.
摘要翻译：具有感测触发器的存储器件，其在耦合到可用时接收地址，并且当感测触发器接收到地址时，将感测触发信号置于感测触发器。存储器件还具有N / N或N输入逻辑门，其提供额外的保证，即当解码地址时不超过一个字线被断言。存储器件还具有N输出或1-N输出驱动器逻辑门，其提供直接用于提供给另一（N-Nary）1-N逻辑门的输出信号。

8. 发明授权

US6046931A Method and apparatus for a RAM circuit having N-nary output interface 有权
标题翻译：具有N个输出接口的RAM电路的方法和装置
公开(公告)号：US6046931A
公开(公告)日：2000-04-04
申请号：US150258
申请日：1998-09-09
申请人： Stephen C. Horne , Michael R. Seningen , James S. Blomgren
发明人： Stephen C. Horne , Michael R. Seningen , James S. Blomgren
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21
CPC分类号： H03K19/0813 , G06F1/08 , G06F17/5045 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/49 , G06F7/5443 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0963 , H03K19/215 , G06F2207/3824 , G06F7/483 , G06F7/508 , G11C7/1006
摘要： A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-nary, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-nary, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-nary) 1-of-N logic gate.
摘要翻译：具有感测触发器的存储器件，其在耦合到可用时接收地址，并且当感测触发器接收到地址时，将感测触发信号置于感测触发器。存储器件还具有N / N或N输入逻辑门，其提供额外的保证，即当解码地址时不超过一个字线被断言。存储器件还具有N输出或1-N输出驱动器逻辑门，其提供直接用于提供给另一（N-Nary）1-N逻辑门的输出信号。

9. 发明授权

US06181596B2 Method and apparatus for a RAM circuit having N-Nary output interface 有权
标题翻译：具有N-Nary输出接口的RAM电路的方法和装置
公开(公告)号：US06181596B2
公开(公告)日：2001-01-30
申请号：US09458766
申请日：1999-12-10
申请人： Stephen C. Horne , Michael R. Seningen , James S. Blomgren
发明人： Stephen C. Horne , Michael R. Seningen , James S. Blomgren
IPC分类号： G11C1156
CPC分类号： H03K19/0813 , G06F1/08 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0963 , H03K19/215
摘要： A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-NARY, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-NARY, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-NARY) 1-of-N logic gate.
摘要翻译：具有感测触发器的存储器件，其在耦合到可用时接收地址，并且当感测触发器接收到地址时，将感测触发信号置于感测触发器。存储器件还具有N-NARY或1-N输入逻辑门，其提供额外的保证，即当解码地址时不超过一个字线被断言。存储器件还具有N-NARY或1-N输出驱动器逻辑门，其提供直接用于提供给另一（N-NARY）1-N逻辑门的输出信号。

10. 发明授权

US6124735A Method and apparatus for a N-nary logic circuit using capacitance isolation 有权
标题翻译：使用电容隔离的N-Nary逻辑电路的方法和装置
公开(公告)号：US6124735A
公开(公告)日：2000-09-26
申请号：US209967
申请日：1998-12-10
申请人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
发明人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21 , H03K19/094
CPC分类号： G11C8/00 , G06F1/08 , G06F17/5045 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/49 , G06F7/5443 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/10 , G11C8/16 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215 , G06F2207/3824 , G06F7/483 , G06F7/508 , G11C7/1006
摘要： The present invention comprises a logic device with improved capacitance isolation and a design methodology for reducing unwanted parasitic capacitance in logic circuits. The logic device further comprises an output signal having a first internal evaluate node and a second evaluate node. Additionally, the logic device comprises a first input signal that has a first input wire and a second input wire where the first input wire corresponds to a first possible value of the first input signal and the second input wire corresponds to a second possible value of the first input signal. The logic device further comprises a first plurality of intermediate nodes that includes a first intermediate node. Additionally, the logic device includes a first plurality of transistors that further includes a first transistor coupling the first internal evaluate node to the first intermediate node and being gated by the first wire of the first input signal. And finally, the logic device of the present invention includes a second transistor that couples the second internal evaluate node to the first intermediate node that is gated by the second wire of the first input signal. At most, one of the first internal evaluate node and the second internal evaluate node couples to the first intermediate node with the second transistor substantially preventing residual charge on the second internal evaluate node from being passed to the first intermediate node when the first input value corresponds to the first possible value.
摘要翻译：本发明包括具有改进的电容隔离的逻辑器件和用于减少逻辑电路中的不想要的寄生电容的设计方法。逻辑装置还包括具有第一内部评估节点和第二评估节点的输出信号。另外，逻辑器件包括具有第一输入线和第二输入线的第一输入信号，其中第一输入线对应于第一输入信号的第一可能值，而第二输入线对应于第一输入线的第二可能值第一输入信号。逻辑设备还包括包括第一中间节点的第一多个中间节点。此外，逻辑器件包括第一多个晶体管，其还包括将第一内部评估节点耦合到第一中间节点并由第一输入信号的第一线选通的第一晶体管。最后，本发明的逻辑器件包括第二晶体管，其将第二内部评估节点耦合到由第一输入信号的第二线选通的第一中间节点。最多的是，第一内部评估节点和第二内部评估节点之一耦合到第一中间节点，其中第二晶体管基本上防止第二内部评估节点上的剩余电荷被传递到第一中间节点，当第一输入值对应于到第一个可能的值。

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