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1. 发明申请

US20070034777A1 Image sensor employing a plurality of photodetector arrays and/or rear-illuminated architecture 有权
标题翻译：采用多个光电检测器阵列和/或背照式结构的图像传感器
公开(公告)号：US20070034777A1
公开(公告)日：2007-02-15
申请号：US11317207
申请日：2005-12-23
申请人： David Tuckerman , Kenneth Honer , Bruce McWilliams , Nicholas Colella , Charles Goudge
发明人： David Tuckerman , Kenneth Honer , Bruce McWilliams , Nicholas Colella , Charles Goudge
IPC分类号： H01L27/00 , H01L31/00
CPC分类号： H04N5/2257 , H01L27/14618 , H01L27/14621 , H01L27/14632 , H01L2924/0002 , H04N5/3415 , H04N9/045 , H04N9/09 , H01L2924/00
摘要： Image sensors are provided having a plurality of photodetectors in a detector layer Optionally, an optically transparent substrate is provided for a rear-illuminated sensor architecture. The photodetectors may be arranged in three or more arrays. Typically, each array is contiguous and is associated with light of a different color and/or wavelength. In addition, the arrays may be coplanar, or, in the alternative, located at increasing distances from a light-receiving surface in an at least partially nonoverlapping manner. Also provided are image sensor packages.
摘要翻译：提供了在检测器层中具有多个光电检测器的图像传感器。可选地，为背照式传感器架构提供光学透明基板。光电检测器可以被布置成三个或更多个阵列。通常，每个阵列是连续的并且与不同颜色和/或波长的光相关联。此外，阵列可以是共面的，或者在替代方案中，以至少部分不重叠的方式位于与光接收表面增加的距离处。还提供了图像传感器封装。

2. 发明申请

US20050082653A1 Structure and method of making sealed capped chips 有权
标题翻译：密封盖片的结构和方法
公开(公告)号：US20050082653A1
公开(公告)日：2005-04-21
申请号：US10948976
申请日：2004-09-24
申请人： Bruce McWilliams , Giles Humpston , Belgacem Haba , David Tuckerman
发明人： Bruce McWilliams , Giles Humpston , Belgacem Haba , David Tuckerman
IPC分类号： H01L21/60 , H01L23/04 , H01L23/10 , H01L23/485 , H01L27/146 , H03H3/007 , H03H3/08 , H03H9/10 , H01L23/02
CPC分类号： H01L23/3114 , B81B2207/095 , B81C1/00293 , B81C1/00301 , B81C2203/0118 , B81C2203/0145 , B81C2203/019 , H01L21/76898 , H01L23/04 , H01L24/11 , H01L24/13 , H01L24/48 , H01L27/14618 , H01L27/14627 , H01L27/14636 , H01L33/62 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13169 , H01L2224/1401 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/48247 , H01L2224/484 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01061 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/16151 , H01L2924/16195 , H01L2924/16235 , H01L2924/3011 , H01L2924/3025 , H03H3/007 , H03H9/0547 , H03H9/0585 , H03H9/059 , H03H9/1057 , H03H9/1064 , H03H9/1071 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element; and (b) forming ring seals surrounding regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through openings in the first element. A chip is provided which includes: (a) a body defining a front surface and one or more circuit elements on or within the body; (b) one or more bond pads exposed at the front surface in a bond pad region; and (c) a metallic ring exposed at the front surface, the ring substantially surrounding the bond pad region. Sealed chip assemblies are formed by sealing an array of the chips, e.g., in wafer form, to a cap element.
摘要翻译：提供了一种制造多个密封组件的方法，其包括：a）将第一元件组装到第二元件，使得第一元件的底表面向下朝向第二元件的前表面并且第一元件的顶表面面向上远离第二元件; 以及（b）通过从第一元件的顶表面通过第一元件中的开口引入第一元件和第二元件之间的可流动材料，形成围绕第二元件的前表面的区域的环形密封件。提供了一种芯片，其包括：（a）主体，其在身体上或体内限定前表面和一个或多个电路元件; （b）在接合焊盘区域中的前表面处暴露的一个或多个接合焊盘; 和（c）在前表面露出的金属环，所述环基本上围绕所述接合焊盘区域。密封的芯片组件通过将芯片的阵列（例如，晶片形式）密封到盖元件来形成。

3. 发明申请

US20080032457A1 Structure and method of making sealed capped chips 审中-公开
标题翻译：密封盖片的结构和方法
公开(公告)号：US20080032457A1
公开(公告)日：2008-02-07
申请号：US11904477
申请日：2007-09-27
申请人： Bruce McWilliams , Giles Humpston , Belgacem Haba , David Tuckerman
发明人： Bruce McWilliams , Giles Humpston , Belgacem Haba , David Tuckerman
IPC分类号： H01L21/00
CPC分类号： H01L23/3114 , B81B2207/095 , B81C1/00293 , B81C1/00301 , B81C2203/0118 , B81C2203/0145 , B81C2203/019 , H01L21/76898 , H01L23/04 , H01L24/11 , H01L24/13 , H01L24/48 , H01L27/14618 , H01L27/14627 , H01L27/14636 , H01L33/62 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13169 , H01L2224/1401 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/48247 , H01L2224/484 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01061 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/16151 , H01L2924/16195 , H01L2924/16235 , H01L2924/3011 , H01L2924/3025 , H03H3/007 , H03H9/0547 , H03H9/0585 , H03H9/059 , H03H9/1057 , H03H9/1064 , H03H9/1071 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element; and (b) forming ring seals surrounding regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through openings in the first element. A chip is provided which includes: (a) a body defining a front surface and one or more circuit elements on or within the body; (b) one or more bond pads exposed at the front surface in a bond pad region; and (c) a metallic ring exposed at the front surface, the ring substantially surrounding the bond pad region. Sealed chip assemblies are formed by sealing an array of the chips, e.g., in wafer form, to a cap element.
摘要翻译：提供了一种制造多个密封组件的方法，其包括：a）将第一元件组装到第二元件，使得第一元件的底表面向下朝向第二元件的前表面并且第一元件的顶表面面向上远离第二元件; 以及（b）通过从第一元件的顶表面通过第一元件中的开口引入第一元件和第二元件之间的可流动材料，形成围绕第二元件的前表面的区域的环形密封件。提供了一种芯片，其包括：（a）主体，其在身体上或体内限定前表面和一个或多个电路元件; （b）在接合焊盘区域中的前表面处暴露的一个或多个接合焊盘; 和（c）在前表面露出的金属环，所述环基本上围绕所述接合焊盘区域。密封的芯片组件通过将芯片的阵列（例如，晶片形式）密封到盖元件来形成。

4. 发明申请

US20050095835A1 Structure and method of making capped chips having vertical interconnects 审中-公开
标题翻译：制造具有垂直互连的封盖芯片的结构和方法
公开(公告)号：US20050095835A1
公开(公告)日：2005-05-05
申请号：US10949674
申请日：2004-09-24
申请人： Giles Humpston , David Tuckerman , Bruce McWilliams , Belgacem Haba , Craig Mitchell
发明人： Giles Humpston , David Tuckerman , Bruce McWilliams , Belgacem Haba , Craig Mitchell
IPC分类号： H01L21/60 , H01L23/04 , H01L23/10 , H01L23/485 , H01L27/146 , H03H3/007 , H03H3/08 , H03H9/10 , H01L21/48
CPC分类号： H01L23/3114 , B81B2207/095 , B81C1/00293 , B81C1/00301 , B81C2203/0118 , B81C2203/0145 , B81C2203/019 , H01L21/76898 , H01L23/04 , H01L24/11 , H01L24/13 , H01L24/48 , H01L27/14618 , H01L27/14627 , H01L27/14636 , H01L33/62 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13169 , H01L2224/1401 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/48247 , H01L2224/484 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01061 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/16151 , H01L2924/16195 , H01L2924/16235 , H01L2924/3011 , H01L2924/3025 , H03H3/007 , H03H9/0547 , H03H9/0585 , H03H9/059 , H03H9/1057 , H03H9/1064 , H03H9/1071 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.
摘要翻译：提供了覆盖芯片和形成封盖芯片的方法，其中电互连通过至少部分地通过盖的多个通孔从芯片的焊盘延伸的导电元件制成。电互连可以是固体的，以便形成延伸穿过通孔的密封件。在一些情况下，螺柱凸起从接合焊盘延伸，形成电互连的部分。在一些情况下，可熔导电介质形成电互连的一部分。

5. 发明申请

US20070096311A1 Structure and method of making capped chips having vertical interconnects 审中-公开
标题翻译：制造具有垂直互连的封盖芯片的结构和方法
公开(公告)号：US20070096311A1
公开(公告)日：2007-05-03
申请号：US11641152
申请日：2006-12-19
申请人： Giles Humpston , David Tuckerman , Bruce McWilliams , Belgacem Haba , Craig Mitchell
发明人： Giles Humpston , David Tuckerman , Bruce McWilliams , Belgacem Haba , Craig Mitchell
IPC分类号： H01L23/48
CPC分类号： H01L23/3114 , B81B2207/095 , B81C1/00293 , B81C1/00301 , B81C2203/0118 , B81C2203/0145 , B81C2203/019 , H01L21/76898 , H01L23/04 , H01L24/11 , H01L24/13 , H01L24/48 , H01L27/14618 , H01L27/14627 , H01L27/14636 , H01L33/62 , H01L2224/0401 , H01L2224/05624 , H01L2224/05644 , H01L2224/11 , H01L2224/11334 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13169 , H01L2224/1401 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/4824 , H01L2224/48247 , H01L2224/484 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01061 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/16151 , H01L2924/16195 , H01L2924/16235 , H01L2924/3011 , H01L2924/3025 , H03H3/007 , H03H9/0547 , H03H9/0585 , H03H9/059 , H03H9/1057 , H03H9/1064 , H03H9/1071 , H01L2924/00 , H01L2924/00012 , H01L2224/45099
摘要： Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.
摘要翻译：提供了覆盖芯片和形成封盖芯片的方法，其中电互连通过至少部分地通过盖的多个通孔从芯片的焊盘延伸的导电元件制成。电互连可以是固体的，以便形成延伸穿过通孔的密封件。在一些情况下，螺柱凸起从接合焊盘延伸，形成电互连的部分。在一些情况下，可熔导电介质形成电互连的一部分。

6. 发明授权

US08995204B2 Circuit devices and methods having adjustable transistor body bias 有权
标题翻译：具有可调节晶体管体偏置的电路器件和方法
公开(公告)号：US08995204B2
公开(公告)日：2015-03-31
申请号：US13167625
申请日：2011-06-23
申请人： Lawrence T. Clark , Bruce McWilliams , Robert Rogenmoser
发明人： Lawrence T. Clark , Bruce McWilliams , Robert Rogenmoser
IPC分类号： G11C7/00 , G11C11/412
CPC分类号： G11C11/412
摘要： Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.
摘要翻译：公开了电路，集成电路器件和方法，其可以包括具有位于栅极下方的屏蔽区域并通过半导体层与栅极分离的可偏置晶体管。偏置电压可以应用于这样的屏蔽区域以优化多个性能特征，例如速度和电流泄漏。特定实施例可以包括耦合在高电源电压和低电源电压之间的偏置部分，每个具有可偏置晶体管。一个或多个发电电路可以产生多个偏置电压。偏置控制部分可以将不同偏置电压之一耦合到可偏置晶体管的屏蔽区域，以提供用于这种最小速度的最小速度和最小电流泄漏。

7. 发明申请

US20070138644A1 Structure and method of making capped chip having discrete article assembled into vertical interconnect 审中-公开
标题翻译：将具有离散制品的封盖芯片组装成垂直互连的结构和方法
公开(公告)号：US20070138644A1
公开(公告)日：2007-06-21
申请号：US11300900
申请日：2005-12-15
申请人： Bruce McWilliams , Giles Humpston , Belgacem Haba , Robert Burtzlaff
发明人： Bruce McWilliams , Giles Humpston , Belgacem Haba , Robert Burtzlaff
IPC分类号： H01L23/48
CPC分类号： B81C1/00301 , B81B2207/095 , H01L27/14618 , H01L27/14636 , H01L2224/48091 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/3011 , H03H3/007 , H03H9/1092 , H01L2924/00014 , H01L2924/00
摘要： A capped chip is provided which includes a chip having a front surface, a plurality of conductive features exposed at the front surface and a cap. The cap has an inner surface facing the front surface of the chip, an outer surface opposite the inner surface, and a through hole extending from the outer surface to the inner surface. A conductive interconnect extends at least partially through the through hole. The interconnect includes a conductive article which occupies a substantial portion of a volume of the interconnect and the interconnect further includes a flowable conductive medium which joins the conductive article to at least one of the plurality of conductive features of the chip or to the cap.
摘要翻译：提供了一种封盖芯片，其包括具有前表面的芯片，在前表面处暴露的多个导电特征和盖。盖具有面向芯片的前表面的内表面，与内表面相对的外表面，以及从外表面延伸到内表面的通孔。导电互连件至少部分延伸穿过通孔。互连件包括占据互连体积的主要部分的导电制品，并且互连件还包括将导电制品连接到芯片的多个导电特征中的至少一个或帽的至少一个的可流动导电介质。

8. 发明授权

US06891255B2 Microelectronic packages having an array of resilient leads 失效
标题翻译：具有弹性引线阵列的微电子封装
公开(公告)号：US06891255B2
公开(公告)日：2005-05-10
申请号：US10408338
申请日：2003-04-07
申请人： John W. Smith , Bruce McWilliams
发明人： John W. Smith , Bruce McWilliams
IPC分类号： G01R1/04 , H01L21/56 , H01L23/31 , H01L23/485 , H01L23/498 , H01L23/495 , H01L23/48 , H01L23/52
CPC分类号： H01L24/28 , G01R1/0483 , H01L21/563 , H01L23/3107 , H01L23/49811 , H01L23/49822 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03001 , H01L2224/0311 , H01L2224/03334 , H01L2224/0384 , H01L2224/0401 , H01L2224/05016 , H01L2224/05022 , H01L2224/05556 , H01L2224/05567 , H01L2224/05572 , H01L2224/13 , H01L2224/13022 , H01L2224/13111 , H01L2224/73203 , H01L2224/83102 , H01L2224/92125 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： A connection component including a flexible substrate having a top surface and a bottom surface, a layer of a compliant, dielectric material overlying the top surface of the substrate, the compliant material layer having a top surface remote from the substrate, an array of flexible, conductive leads having first ends attached to terminals accessible at the bottom surface of the substrate and second ends adjacent the top surface of the compliant layer, wherein each lead comprises a core of a first conductive material surrounded by a layer of a second conductive material, the second conductive material having a greater yield strength than the first conductive material.
摘要翻译：一种连接部件，包括具有顶表面和底表面的柔性基底，覆盖在基底顶表面上的顺应性电介质材料层，柔顺材料层具有远离基底的顶表面，柔性的，导电引线具有附接到在基板的底表面可接近的端子的第一端和与柔性层的顶表面相邻的第二端，其中每个引线包括由第二导电材料层包围的第一导电材料的芯，第二导电材料具有比第一导电材料更大的屈服强度。

9. 发明申请

US20120327725A1 CIRCUIT DEVICES AND METHODS HAVING ADJUSTABLE TRANSISTOR BODY BIAS 有权
标题翻译：具有可调节晶体管体偏置的电路装置和方法
公开(公告)号：US20120327725A1
公开(公告)日：2012-12-27
申请号：US13167625
申请日：2011-06-23
申请人： Lawrence T. Clark , Bruce McWilliams , Robert Rogenmoser
发明人： Lawrence T. Clark , Bruce McWilliams , Robert Rogenmoser
IPC分类号： G11C7/00 , G05F1/10
CPC分类号： G11C11/412
摘要： Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.
摘要翻译：公开了电路，集成电路器件和方法，其可以包括具有位于栅极下方的屏蔽区域并通过半导体层与栅极分离的可偏置晶体管。偏置电压可以应用于这样的屏蔽区域以优化多个性能特征，例如速度和电流泄漏。特定实施例可以包括耦合在高电源电压和低电源电压之间的偏置部分，每个具有可偏置晶体管。一个或多个发电电路可以产生多个偏置电压。偏置控制部分可以将不同偏置电压之一耦合到可偏置晶体管的屏蔽区域，以提供用于这种最小速度的最小速度和最小电流泄漏。

10. 发明申请

US20080118241A1 Control of stray light in camera systems employing an optics stack and associated methods 审中-公开
标题翻译：使用光学堆栈和相关方法控制相机系统中的杂散光
公开(公告)号：US20080118241A1
公开(公告)日：2008-05-22
申请号：US11600282
申请日：2006-11-16
申请人： Robert TeKolste , Bruce McWilliams , Hongtao Han , William Hudson Welch
发明人： Robert TeKolste , Bruce McWilliams , Hongtao Han , William Hudson Welch
IPC分类号： G03B17/00
CPC分类号： G02B27/0018 , H01L27/14618 , H01L2224/48091 , H04N5/2254 , H04N5/2257 , H01L2924/00014
摘要： A camera system may include an optics stack including two substrates secured together in a vertical direction and an optical system on the two substrates, the two substrates having exposed sides, a detector on a detector substrate, and a stray light blocker directly on at least some sides of the optics stack.
摘要翻译：相机系统可以包括光学叠层，其包括在垂直方向上固定在一起的两个基板和两个基板上的光学系统，两个基板具有暴露的侧面，检测器基板上的检测器和至少一些光学堆叠的两侧。

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