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1. 发明申请

US20100058107A1 Error recovery within processing stages of an integrated circuit 有权
标题翻译：集成电路处理阶段内的错误恢复
公开(公告)号：US20100058107A1
公开(公告)日：2010-03-04
申请号：US12461740
申请日：2009-08-21
申请人： David Theodore Blaauw , Shidhartha Das , Todd Michael Austin
发明人： David Theodore Blaauw , Shidhartha Das , Todd Michael Austin
IPC分类号： G06F11/07
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

2. 发明授权

US08060814B2 Error recovery within processing stages of an integrated circuit 有权
标题翻译：集成电路处理阶段内的错误恢复
公开(公告)号：US08060814B2
公开(公告)日：2011-11-15
申请号：US12461740
申请日：2009-08-21
申请人： David Theodore Blaauw , Shidhartha Das , Todd Michael Austin
发明人： David Theodore Blaauw , Shidhartha Das , Todd Michael Austin
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

3. 发明授权

US08185812B2 Single event upset error detection within an integrated circuit 有权
标题翻译：集成电路内的单事件镦粗错误检测
公开(公告)号：US08185812B2
公开(公告)日：2012-05-22
申请号：US11636716
申请日：2006-12-11
申请人： Shidhartha Das , David Theodore Blaauw , David Michael Bull
发明人： Shidhartha Das , David Theodore Blaauw , David Michael Bull
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.
摘要翻译：集成电路2包括逻辑电路10和顺序存储元件8.逻辑电路10和顺序存储元件8都可能经受粒子撞击，从而引起单事件失真错误。可以通过检测在与该顺序存储元件8相关联的有效过渡时段之外发生的顺序存储元件8存储的存储值中的转变来检测这些单事件中断错误。

4. 发明授权

US08006147B2 Error detection in precharged logic 有权
标题翻译：预充电逻辑中的误差检测
公开(公告)号：US08006147B2
公开(公告)日：2011-08-23
申请号：US12382427
申请日：2009-03-16
申请人： David Michael Bull , Shidhartha Das , David Theodore Blaauw
发明人： David Michael Bull , Shidhartha Das , David Theodore Blaauw
IPC分类号： G11C29/00
CPC分类号： G01R31/3177
摘要： An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译：集成电路提供有多米诺逻辑，包括推测节点和检查器节点。预充电电路对推测节点和检查器节点进行预充电。逻辑电路根据输入信号值为推测节点和校验器节点提供放电路径。评估控制电路首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路的输入信号具有适当的值，则它们可以被放电。当推测节点和检查器节点都不是放电或未放电的两者之一时，错误检测电路检测到错误。

5. 发明授权

US08103922B2 Error detection in precharged logic 有权
标题翻译：预充电逻辑中的误差检测
公开(公告)号：US08103922B2
公开(公告)日：2012-01-24
申请号：US13162308
申请日：2011-06-16
申请人： David Michael Bull , Shidhartha Das , David Theodore Blaauw
发明人： David Michael Bull , Shidhartha Das , David Theodore Blaauw
IPC分类号： G11C29/00
CPC分类号： G01R31/3177
摘要： An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译：集成电路提供有多米诺逻辑，包括推测节点和检查器节点。预充电电路对推测节点和检查器节点进行预充电。逻辑电路根据输入信号值为推测节点和校验器节点提供放电路径。评估控制电路首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路的输入信号具有适当的值，则它们可以被放电。当推测节点和检查器节点都不是放电或未放电的两者之一时，错误检测电路检测到错误。

6. 发明申请

US20110246843A1 ERROR DETECTION IN PRECHARGED LOGIC 有权
标题翻译：预置逻辑中的错误检测
公开(公告)号：US20110246843A1
公开(公告)日：2011-10-06
申请号：US13162308
申请日：2011-06-16
申请人： David Michael BULL , Shidhartha Das , David Theodore Blaauw
发明人： David Michael BULL , Shidhartha Das , David Theodore Blaauw
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177
摘要： An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译：集成电路提供有多米诺逻辑，包括推测节点和检查器节点。预充电电路对推测节点和检查器节点进行预充电。逻辑电路根据输入信号值为推测节点和校验器节点提供放电路径。评估控制电路首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路的输入信号具有适当的值，则它们可以被放电。当推测节点和检查器节点都不是放电或未放电的两者之一时，错误检测电路检测到错误。

7. 发明申请

US20100235697A1 Error detection in precharged logic 有权
标题翻译：预充电逻辑中的误差检测
公开(公告)号：US20100235697A1
公开(公告)日：2010-09-16
申请号：US12382427
申请日：2009-03-16
申请人： David Michael Bull , Shidhartha Das , David Theodore Blaauw
发明人： David Michael Bull , Shidhartha Das , David Theodore Blaauw
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177
摘要： An integrated circuit 2 is provided with domino logic including a speculative node 22 and a checker node 24. Precharged circuitry 36 precharges both the speculative node and the checker node. Logic circuitry 26 provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry 28, 30 first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry 26 have appropriate values. Error detection circuitry 32 detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译：集成电路2具有包括推测节点22和检验器节点24的多米诺逻辑逻辑。预充电电路36对推测节点和检验器节点进行预充电。逻辑电路26根据输入信号值提供推测节点和校验器节点的放电路径。评估控制电路28,30首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路26的输入信号具有适当的值，则它们可以被放电。错误检测电路32在推测节点和检查器节点都不是放电的两者之一或两者未被充电时检测错误。

8. 发明授权

US07263015B2 Address decoding 有权
标题翻译：地址解码
公开(公告)号：US07263015B2
公开(公告)日：2007-08-28
申请号：US11267574
申请日：2005-11-07
申请人： David Theodore Blaauw , David Michael Bull , Shidhartha Das
发明人： David Theodore Blaauw , David Michael Bull , Shidhartha Das
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/418 , G11C8/08 , G11C8/10
摘要： A signal capture element for providing a first pre-charged logic level as first and second interim address portion signals during a pre-charged period and outputting during an evaluate period an address portion logic level as the first interim address portion signal and an inverted address portion logic level as the second interim address portion signal. First and second address portion signals are derivable respectively from first and second interim address portion signals. An inverter circuit for outputting to an address decoder during a pre-charged period a second pre-charged logic level as the first and second address portion signals. The inverter circuit having transfer characteristics that maintain voltage levels such that the first and second address portion signals are interpreted to be at the second pre-charged logic level despite the first or second interim address portion signal failing to transition to a valid logic level during the evaluate period.
摘要翻译：一种信号捕捉元件，用于在预充电周期期间提供第一预充电逻辑电平作为第一和第二中间地址部分信号，并且在评估周期期间输出地址部分逻辑电平作为第一中间地址部分信号和反相地址部分逻辑电平作为第二临时地址部分信号。第一和第二地址部分信号可以分别从第一和第二临时地址部分信号导出。一种逆变器电路，用于在预充电周期期间将作为第一和第二地址部分信号的第二预充电逻辑电平输出到地址译码器。逆变器电路具有保持电压电平的传输特性，使得第一和第二地址部分信号被解释为处于第二预充电逻辑电平，尽管第一或第二临时地址部分信号在期间不能转换到有效逻辑电平评估期

9. 发明授权

US08650470B2 Error recovery within integrated circuit 有权
标题翻译：集成电路内的错误恢复
公开(公告)号：US08650470B2
公开(公告)日：2014-02-11
申请号：US12926084
申请日：2010-10-25
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , David Bull
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/00 , G06F11/0706 , G06F11/0736 , G06F11/0754 , G06F11/0757 , G06F11/079 , G06F11/1402 , G06F11/1604
摘要： An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.
摘要翻译：集成电路包括具有错误检测和误差校正电路的一个或多个部分，并且其操作参数给出有限的非零误码率以及形成和操作以提供零错误率的一个或多个部分。

10. 发明授权

US08407537B2 Error recover within processing stages of an integrated circuit 有权
标题翻译：在集成电路的处理阶段内发生错误恢复
公开(公告)号：US08407537B2
公开(公告)日：2013-03-26
申请号：US12923908
申请日：2010-10-13
申请人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
IPC分类号： G06F1/08 , G06F11/30
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译：集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自处理逻辑1014处于非延迟捕获时间。在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换值。非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播在重新启动时钟之前通过后续的处理逻辑。调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

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