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1. 发明授权

US07426215B2 Method and apparatus for scheduling packets 有权
标题翻译：调度数据包的方法和装置
公开(公告)号：US07426215B2
公开(公告)日：2008-09-16
申请号：US10819428
申请日：2004-04-06
申请人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
发明人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
IPC分类号： H04L12/28
CPC分类号： H04L47/568 , H04L47/50 , H04L47/527
摘要： A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for transmission, the packet's transmission round and relative position within that round are determined, and an identifier for the packet is placed at the appropriate position within the scheduling array. A bit of the associated smoothing register is set, the set bit corresponding to the entry receiving the packet identifier. During transmission, the set bits of the smoothing register associated with a current round buffer are read to identify packets that are to be dequeued.
摘要翻译：一种使用具有一个或多个平滑寄存器的预排序调度阵列来调度分组的方法和装置。调度阵列包括多个循环缓冲器，每个循环缓冲器具有相关联的平滑寄存器。为了调度分组进行传输，确定分组在该轮次内的传输轮和相对位置，并且将分组的标识符放置在调度阵列内的适当位置。设置相关平滑寄存器的一位，该设置位对应于接收分组标识符的条目。在传输期间，读取与当前循环缓冲器相关联的平滑寄存器的置位，以识别要出列的分组。

2. 发明申请

US20050220115A1 Method and apparatus for scheduling packets 审中-公开
标题翻译：调度数据包的方法和装置
公开(公告)号：US20050220115A1
公开(公告)日：2005-10-06
申请号：US10819818
申请日：2004-04-06
申请人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
发明人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
IPC分类号： H04L12/56
CPC分类号： H04L49/90
摘要： A method and apparatus for scheduling packets using one or more pre-sort scheduling arrays. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. Packets may be scheduled according to a non-work conserving technique, or packets may be scheduled according to a work conserving technique. A packet is transmitted by dequeuing the packet from a pre-sorted scheduling array.
摘要翻译：一种用于使用一个或多个预排序调度阵列来调度分组的方法和装置。当分组被接收时进行分组的调度决定，并且接收的分组的条目存储在预先排序的调度数组中。可以根据非工作节省技术来调度分组，或者可以根据工作节省技术来安排分组。通过从预先排序的调度数组中排队该分组来传送分组。

3. 发明申请

US20050220114A1 Method and apparatus for scheduling packets 有权
标题翻译：调度数据包的方法和装置
公开(公告)号：US20050220114A1
公开(公告)日：2005-10-06
申请号：US10819428
申请日：2004-04-06
申请人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
发明人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
IPC分类号： H04L12/56
CPC分类号： H04L47/568 , H04L47/50 , H04L47/527
摘要： A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for transmission, the packet's transmission round and relative position within that round are determined, and an identifier for the packet is placed at the appropriate position within the scheduling array. A bit of the associated smoothing register is set, the set bit corresponding to the entry receiving the packet identifier. During transmission, the set bits of the smoothing register associated with a current round buffer are read to identify packets that are to be dequeued.
摘要翻译：一种使用具有一个或多个平滑寄存器的预排序调度阵列来调度分组的方法和装置。调度阵列包括多个循环缓冲器，每个循环缓冲器具有相关联的平滑寄存器。为了调度分组进行传输，确定分组在该轮次内的传输轮和相对位置，并且将分组的标识符放置在调度阵列内的适当位置。设置相关平滑寄存器的一位，该设置位对应于接收分组标识符的条目。在传输期间，读取与当前循环缓冲器相关联的平滑寄存器的设置位以识别要出列的分组。

4. 发明授权

US07522620B2 Method and apparatus for scheduling packets 失效
标题翻译：调度数据包的方法和装置
公开(公告)号：US07522620B2
公开(公告)日：2009-04-21
申请号：US10640206
申请日：2003-08-12
申请人： John Wishneusky , Sanjeev Jain , David Romano
发明人： John Wishneusky , Sanjeev Jain , David Romano
IPC分类号： H04L12/56
CPC分类号： H04L47/6215 , H04L47/50 , H04L47/527 , H04L47/6225
摘要： A method and apparatus for scheduling packets using a pre-sort deficit round-robin method. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. A packet is transmitted by dequeuing the packet from the pre-sorted scheduling array.
摘要翻译：一种使用预排序缺陷循环方法来调度分组的方法和装置。当分组被接收时进行分组的调度决定，并且接收的分组的条目存储在预先排序的调度数组中。通过从预先排序的调度数组中排队数据包来发送数据包。

5. 发明申请

US20050036495A1 Method and apparatus for scheduling packets 失效
标题翻译：调度数据包的方法和装置
公开(公告)号：US20050036495A1
公开(公告)日：2005-02-17
申请号：US10640206
申请日：2003-08-12
申请人： John Wishneusky , Sanjeev Jain , David Romano
发明人： John Wishneusky , Sanjeev Jain , David Romano
IPC分类号： H04L12/56
CPC分类号： H04L47/6215 , H04L47/50 , H04L47/527 , H04L47/6225
摘要： A method and apparatus for scheduling packets using a pre-sort deficit round-robin method. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. A packet is transmitted by dequeuing the packet from the pre-sorted scheduling array.
摘要翻译：一种使用预排序缺陷循环方法来调度分组的方法和装置。当分组被接收时进行分组的调度决定，并且接收的分组的条目存储在预先排序的调度数组中。通过从预先排序的调度数组中排队数据包来发送数据包。

6. 发明授权

US07243214B2 Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessary 失效
标题翻译：分阶段处理器流水线的失速优化，分析当前和下一个指令以确定是否需要停机
公开(公告)号：US07243214B2
公开(公告)日：2007-07-10
申请号：US10419360
申请日：2003-04-21
申请人： Niall D. McDonnell , John Wishneusky
发明人： Niall D. McDonnell , John Wishneusky
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/3867 , G06F9/3873
摘要： According to some embodiments, a method determining a number of stages associated with an instruction to be executed via a processor pipeline, determining a number of stages associated with a subsequent instruction, and stalling the pipeline based on the number of stages associated with the instruction to be executed and the number of stages associated with the subsequent instruction is provided.
摘要翻译：根据一些实施例，确定与经由处理器流水线执行的指令相关联的级数的方法，确定与后续指令相关联的级数，以及基于与指令相关联的级数来停止流水线并且提供与后续指令相关联的级数。

7. 发明授权

US07007156B2 Multiple coprocessor architecture to process a plurality of subtasks in parallel 失效
标题翻译：多个协处理器架构并行处理多个子任务
公开(公告)号：US07007156B2
公开(公告)日：2006-02-28
申请号：US09751943
申请日：2000-12-28
申请人： Gavin J. Stark , John Wishneusky
发明人： Gavin J. Stark , John Wishneusky
IPC分类号： G06F9/00
CPC分类号： G06F9/5044 , G06F2209/5017
摘要： A programmed state processing machine architecture and method that provides improved efficiency for processing data manipulation tasks. In one embodiment, the processing machine comprises a control engine and a plurality coprocessors, a data memory, and an instruction memory. A sequence of instructions having a plurality of portions are issued by the instruction memory, wherein the control engine and each of the processors is caused to perform a specific task based on the portion of the instructions designated for that component. Accordingly, a data manipulation task can be divided into a plurality of subtasks that are processed in parallel by respective processing components in the architecture.
摘要翻译：一种编程状态处理机架构和方法，可提高处理数据操作任务的效率。在一个实施例中，处理机包括控制引擎和多个协处理器，数据存储器和指令存储器。具有多个部分的指令序列由指令存储器发出，其中使控制引擎和每个处理器基于为该部件指定的指令的部分执行特定任务。因此，数据操作任务可以被划分成由架构中的各个处理组件并行处理的多个子任务。

8. 发明授权

US06963535B2 MAC bus interface 失效
标题翻译： MAC总线接口
公开(公告)号：US06963535B2
公开(公告)日：2005-11-08
申请号：US09751936
申请日：2000-12-28
申请人： Gavin J. Stark , John Wishneusky
发明人： Gavin J. Stark , John Wishneusky
IPC分类号： H04L12/413 , H04L12/56 , H04L29/06 , H04L29/08 , H04L12/26
CPC分类号： H04L29/06 , H04L12/40032 , H04L69/324
摘要： A Media Access Control (MAC) Bus interface definition and multiplexor scheme that may be implemented to provide chip layout-insensitive connections between a number of communication physical layer port entities and a single buffer manager or communications controller entity, utilizing a set of independent pipelined buses. The interface comprising three buses: A MAC In Data bus, a MAC Out Data bus, and a MAC Out Message bus. Each bus can operated with an independent set of timing signals to enable data transfers between a system side block and one or more network side blocks. The multiplexor scheme provides a multiplexor for each of the MAC buses, and enables a single system side block to connect to multiple network side blocks. The multiplexors may be also be cascaded.
摘要翻译：媒体访问控制（MAC）总线接口定义和多路复用器方案，其可被实现以在多个通信物理层端口实体与单个缓冲器管理器或通信控制器实体之间提供芯片布局不敏感的连接，利用一组独立的流水线总线。该接口包括三条总线：MAC数据总线，MAC输出数据总线和MAC输出消息总线。每个总线可以用独立的一组定时信号进行操作，以实现系统侧块和一个或多个网络侧块之间的数据传输。多路复用器方案为每个MAC总线提供多路复用器，并使得单个系统侧块能够连接到多个网络侧块。多路复用器也可以级联。

9. 发明授权

US06981113B2 Storage registers for a processor pipeline 失效
标题翻译：处理器管道的存储寄存器
公开(公告)号：US06981113B2
公开(公告)日：2005-12-27
申请号：US10419435
申请日：2003-04-21
申请人： Niall D. McDonnell , John Wishneusky
发明人： Niall D. McDonnell , John Wishneusky
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38 , G06F12/02
CPC分类号： G06F9/30123 , G06F9/3851
摘要： According to some embodiments, storage registers are provided for a processor pipeline.
摘要翻译：根据一些实施例，为处理器流水线提供存储寄存器。

10. 发明授权

US5566352A Register-read acknowledgment and prioritization for integration with a hardware-based interrupt acknowledgment mechanism 失效
标题翻译：与基于硬件的中断确认机制集成的寄存器读取确认和优先级
公开(公告)号：US5566352A
公开(公告)日：1996-10-15
申请号：US774
申请日：1993-01-04
申请人： John Wishneusky
发明人： John Wishneusky
IPC分类号： G06F13/26 , G06F9/00 , G06F9/46
CPC分类号： G06F13/26
摘要： A register-based computer architecture is particularly suited for using a common resource, such as a host processor or CPU, to respond to multiple devices such as co-processors, slave processors, or peripherals via service requests initiated by these devices. The invention's register acknowledgment and service prioritizing features are preferably added to, and integrated with, a prior-art, hardware-based interrupt acknowledgment mechanism, thus providing enhanced flexibility and performance. This architecture includes features for enhancing the support of a service-request based or queue-driven interface between the host processor and the supported devices, including a Service Request Status Register, a Service Request Configuration Register, and Service Request Acknowledge Register(s). From the point of view of the host processor, these registers are accessed as normal input/output read/write operations. From the point of view of the supported devices, such register operations appear to be interrupt acknowledgment operations. This transformation is effected by special-purpose logic within the architecture. The invention is preferably embodied in a monolithic integrated circuit that supports control by the host processor of a potentially large number of data communications ports. These features can be incorporated in pin compatible new versions of existing devices so as to be backwards compatible with the existing devices, thus allowing end users to gracefully upgrade their systems with minimal effort.
摘要翻译：基于寄存器的计算机架构特别适合于使用诸如主机处理器或CPU的公共资源来通过由这些设备发起的服务请求来响应诸如协处理器，从属处理器或外围设备的多个设备。本发明的注册确认和服务优先级特征优选地被添加到现有技术的基于硬件的中断确认机制中并与其集成，从而提供增强的灵活性和性能。该架构包括用于增强在主处理器和所支持的设备之间的基于服务请求或队列驱动的接口的支持的特征，包括服务请求状态寄存器，服务请求配置寄存器和服务请求确认寄存器。从主处理器的角度来看，这些寄存器作为普通输入/输出读/写操作被访问。从支持的设备的角度来看，这种寄存器操作似乎是中断确认操作。这种转换由架构内的专用逻辑实现。本发明优选地体现在支持主处理器对潜在大量数据通信端口的控制的单片集成电路中。这些功能可以并入现有设备的引脚兼容的新版本，以便与现有设备向后兼容，从而允许最终用户以最小的努力平稳地升级其系统。

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