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1. 发明授权

US07426215B2 Method and apparatus for scheduling packets 有权
标题翻译：调度数据包的方法和装置
公开(公告)号：US07426215B2
公开(公告)日：2008-09-16
申请号：US10819428
申请日：2004-04-06
申请人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
发明人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
IPC分类号： H04L12/28
CPC分类号： H04L47/568 , H04L47/50 , H04L47/527
摘要： A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for transmission, the packet's transmission round and relative position within that round are determined, and an identifier for the packet is placed at the appropriate position within the scheduling array. A bit of the associated smoothing register is set, the set bit corresponding to the entry receiving the packet identifier. During transmission, the set bits of the smoothing register associated with a current round buffer are read to identify packets that are to be dequeued.
摘要翻译：一种使用具有一个或多个平滑寄存器的预排序调度阵列来调度分组的方法和装置。调度阵列包括多个循环缓冲器，每个循环缓冲器具有相关联的平滑寄存器。为了调度分组进行传输，确定分组在该轮次内的传输轮和相对位置，并且将分组的标识符放置在调度阵列内的适当位置。设置相关平滑寄存器的一位，该设置位对应于接收分组标识符的条目。在传输期间，读取与当前循环缓冲器相关联的平滑寄存器的置位，以识别要出列的分组。

2. 发明申请

US20050220115A1 Method and apparatus for scheduling packets 审中-公开
标题翻译：调度数据包的方法和装置
公开(公告)号：US20050220115A1
公开(公告)日：2005-10-06
申请号：US10819818
申请日：2004-04-06
申请人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
发明人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
IPC分类号： H04L12/56
CPC分类号： H04L49/90
摘要： A method and apparatus for scheduling packets using one or more pre-sort scheduling arrays. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. Packets may be scheduled according to a non-work conserving technique, or packets may be scheduled according to a work conserving technique. A packet is transmitted by dequeuing the packet from a pre-sorted scheduling array.
摘要翻译：一种用于使用一个或多个预排序调度阵列来调度分组的方法和装置。当分组被接收时进行分组的调度决定，并且接收的分组的条目存储在预先排序的调度数组中。可以根据非工作节省技术来调度分组，或者可以根据工作节省技术来安排分组。通过从预先排序的调度数组中排队该分组来传送分组。

3. 发明申请

US20050220114A1 Method and apparatus for scheduling packets 有权
标题翻译：调度数据包的方法和装置
公开(公告)号：US20050220114A1
公开(公告)日：2005-10-06
申请号：US10819428
申请日：2004-04-06
申请人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
发明人： David Romano , Sanjeev Jain , Gilbert Wolrich , John Wishneusky
IPC分类号： H04L12/56
CPC分类号： H04L47/568 , H04L47/50 , H04L47/527
摘要： A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for transmission, the packet's transmission round and relative position within that round are determined, and an identifier for the packet is placed at the appropriate position within the scheduling array. A bit of the associated smoothing register is set, the set bit corresponding to the entry receiving the packet identifier. During transmission, the set bits of the smoothing register associated with a current round buffer are read to identify packets that are to be dequeued.
摘要翻译：一种使用具有一个或多个平滑寄存器的预排序调度阵列来调度分组的方法和装置。调度阵列包括多个循环缓冲器，每个循环缓冲器具有相关联的平滑寄存器。为了调度分组进行传输，确定分组在该轮次内的传输轮和相对位置，并且将分组的标识符放置在调度阵列内的适当位置。设置相关平滑寄存器的一位，该设置位对应于接收分组标识符的条目。在传输期间，读取与当前循环缓冲器相关联的平滑寄存器的设置位以识别要出列的分组。

4. 发明授权

US07325099B2 Method and apparatus to enable DRAM to support low-latency access via vertical caching 失效
标题翻译：使DRAM能够通过垂直高速缓存支持低延迟访问的方法和装置
公开(公告)号：US07325099B2
公开(公告)日：2008-01-29
申请号：US10974122
申请日：2004-10-27
申请人： Sanjeev Jain , Mark B. Rosenbluth , Matthew Adiletta , Gilbert Wolrich
发明人： Sanjeev Jain , Mark B. Rosenbluth , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： H04L12/2854 , G06F12/0862 , G06F12/0875
摘要： Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store. The scheme provides similar performance to SRAM-based schemes, but uses much cheaper DRAM-type memory.
摘要翻译：实现较慢存储器的方法和装置，例如基于动态随机存取存储器（DRAM）的存储器，以支持使用垂直缓存的低延迟访问。用于包处理功能（包括计量和流量统计）的相关功能元数据存储在外部基于DRAM的存储中。在一个实施例中，DRAM包括双数据速率（DDR）DRAM。公开了一种网络处理器架构，其包括与DRAM控制器耦合的数据高速缓存的DDR辅助。该架构还包括用于执行各种分组处理功能的多个计算引擎。一个这样的功能是DDR辅助功能，其用于预取当前分组的一组功能元数据并将功能元数据存储在数据高速缓存中。随后，一个或多个分组处理功能可以通过从高速缓存访问功能元数据来操作。功能完成后，将功能元数据写回到基于DRAM的商店。该方案提供与基于SRAM的方案类似的性能，但使用更便宜的DRAM型存储器。

5. 发明授权

US07554908B2 Techniques to manage flow control 有权
标题翻译：管理流量控制的技术
公开(公告)号：US07554908B2
公开(公告)日：2009-06-30
申请号：US11009861
申请日：2004-12-10
申请人： Sanjeev Jain , Mark B. Rosenbluth , Gilbert Wolrich , Hugh M. Wilkinson
发明人： Sanjeev Jain , Mark B. Rosenbluth , Gilbert Wolrich , Hugh M. Wilkinson
IPC分类号： G06F11/00 , H04J3/14 , H04L12/26
CPC分类号： H04L47/10 , H04L49/15 , H04L49/254 , H04L49/30 , H04L2012/5678
摘要： Method and apparatus to manage flow control for a network device are described.
摘要翻译：描述了一种用于管理网络设备的流量控制的方法和装置。

6. 发明申请

US20070223504A1 Efficient sort scheme for a hierarchical scheduler 有权
标题翻译：分层调度器的高效排序方案
公开(公告)号：US20070223504A1
公开(公告)日：2007-09-27
申请号：US11389650
申请日：2006-03-23
申请人： Sanjeev Jain , Mark Rosenbluth , Gilbert Wolrich
发明人： Sanjeev Jain , Mark Rosenbluth , Gilbert Wolrich
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L47/50 , H04L47/56 , H04L47/60 , H04L49/901
摘要： Scheduling of packets is performed by a scheduler based on departure times. If wrap up of departure times is possible, departure times are transposed based on a zone associated with the last departure time. By using the zone to transpose in order to sort departure times, cycles of independent checks on each of the departure times are avoided.
摘要翻译：基于出发次数由调度程序执行数据包的调度。如果出发时间结束，可以根据与最后一个出发时间相关的区域进行转机。通过使用区域进行转置以排序出发时间，避免了每个出发时间的独立检查周期。

7. 发明申请

US20070044103A1 Inter-thread communication of lock protected data 审中-公开
标题翻译：锁保护数据的线程间通信
公开(公告)号：US20070044103A1
公开(公告)日：2007-02-22
申请号：US11190115
申请日：2005-07-25
申请人： Mark Rosenbluth , Sanjeev Jain , Gilbert Wolrich
发明人： Mark Rosenbluth , Sanjeev Jain , Gilbert Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/526
摘要： In general, in one aspect, the disclosure describes a method that includes issuing, by a first thread at a first programmable unit of a set of multiple multi-threaded programmable units integrated within a single die, a request for a lock associated with data. The method also includes receiving, by the first thread, a grant for the lock and identification of a second thread to receive a grant for the lock after the lock is released by the first thread. The first thread initiates transfer of the data associated with the lock to the one of the multiple multi-threaded programmable units executing the second thread and releases the lock.
摘要翻译：通常，在一个方面，本公开描述了一种方法，其包括由集成在单个管芯内的一组多个多线程可编程单元的第一可编程单元的第一线程发出与数据相关联的锁定请求。所述方法还包括由所述第一线程接收所述锁的许可和识别第二线程以在所述锁被所述第一线程释放之后接收所述锁的许可。第一线程启动与锁相关联的数据传送到执行第二线程的多个多线程可编程单元之一并释放锁。

8. 发明申请

US20070008985A1 Method and apparatus to support efficient check-point and role-back operations for flow-controlled queues in network devices 有权
标题翻译：支持网络设备流量控制队列的有效检查点和角色返回操作的方法和装置
公开(公告)号：US20070008985A1
公开(公告)日：2007-01-11
申请号：US11173005
申请日：2005-06-30
申请人： Sridhar Lakshmanamurthy , Sanjeev Jain , Gilbert Wolrich , Hugh Wilkinson
发明人： Sridhar Lakshmanamurthy , Sanjeev Jain , Gilbert Wolrich , Hugh Wilkinson
IPC分类号： H04L12/56
CPC分类号： H04L49/557 , H04L49/1523 , H04L49/552 , H04L49/90 , H04L49/901 , H04L49/9063
摘要： Method and apparatus to support efficient check-point and role-back operations for flow-controlled queues in network devices. The method and apparatus employ queue descriptors to manage transfer of data from corresponding queues in memory into a switch fabric. In one embodiment, each queue descriptor includes an enqueue pointer identifying a tail cell of a segment of data scheduled to be transferred from the queue, a schedule pointer identifying a head cell of the segment of data, and a commit pointer identifying a most recent cell in the segment of data to be successfully transmitted into the switch fabric. In another embodiment, the queue descriptor further includes a scheduler sequence number; and a committed sequence number that are employed in connection with transfers of data from queues containing multiple segments. The various pointers and sequence numbers are employed to facilitate efficient check-point and roll-back operations relating to unsuccessful transmissions into the switch fabric.
摘要翻译：支持网络设备流量控制队列的有效检查点和角色返回操作的方法和装置。该方法和装置使用队列描述符来管理数据从存储器中的相应队列传输到交换结构。在一个实施例中，每个队列描述符包括标识被调度为从队列传送的数据段的尾部单元的入队指针，标识数据段的头单元的调度指针以及标识最近的单元的提交指针在数据段中成功发送到交换矩阵中。在另一个实施例中，队列描述符还包括调度器序列号; 以及与从包含多个段的队列传送数据相关联使用的承诺序列号。采用各种指针和序列号来促进与进入交换结构的不成功传输有关的有效的检查点和回滚操作。

9. 发明申请

US20060155959A1 Method and apparatus to provide efficient communication between processing elements in a processor unit 失效
标题翻译：用于在处理器单元中的处理元件之间提供有效通信的方法和装置
公开(公告)号：US20060155959A1
公开(公告)日：2006-07-13
申请号：US11018579
申请日：2004-12-21
申请人： Sanjeev Jain , Gilbert Wolrich , Mark Rosenbluth
发明人： Sanjeev Jain , Gilbert Wolrich , Mark Rosenbluth
IPC分类号： G06F15/00
CPC分类号： G06F13/4252
摘要： A context forwarding bus efficiently communicates control and data between processing elements in a processor unit having a plurality of processing elements. Control and data information is transferred over a first bus from processing element to processing element.
摘要翻译：上下文转发总线在具有多个处理元件的处理器单元中有效地传送处理元件之间的控制和数据。控制和数据信息通过第一总线从处理元件传送到处理元件。

10. 发明申请

US20060090039A1 Method and apparatus to enable DRAM to support low-latency access via vertical caching 失效
标题翻译：使DRAM能够通过垂直高速缓存支持低延迟访问的方法和装置
公开(公告)号：US20060090039A1
公开(公告)日：2006-04-27
申请号：US10974122
申请日：2004-10-27
申请人： Sanjeev Jain , Mark Rosenbluth , Matthew Adiletta , Gilbert Wolrich
发明人： Sanjeev Jain , Mark Rosenbluth , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： H04L12/2854 , G06F12/0862 , G06F12/0875
摘要： Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store. The scheme provides similar performance to SRAM-based schemes, but uses much cheaper DRAM-type memory.
摘要翻译：实现较慢存储器的方法和装置，例如基于动态随机存取存储器（DRAM）的存储器，以支持使用垂直缓存的低延迟访问。用于包处理功能（包括计量和流量统计）的相关功能元数据存储在外部基于DRAM的存储中。在一个实施例中，DRAM包括双数据速率（DDR）DRAM。公开了一种网络处理器架构，其包括与DRAM控制器耦合的数据高速缓存的DDR辅助。该架构还包括用于执行各种分组处理功能的多个计算引擎。一个这样的功能是DDR辅助功能，其用于预取当前分组的一组功能元数据并将功能元数据存储在数据高速缓存中。随后，一个或多个分组处理功能可以通过从高速缓存访问功能元数据来操作。功能完成后，将功能元数据写回到基于DRAM的商店。该方案提供与基于SRAM的方案类似的性能，但使用更便宜的DRAM型存储器。

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