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    • 1. 发明授权
    • ESD protection circuit for I/O buffers
    • 用于I / O缓冲器的ESD保护电路
    • US5953190A
    • 1999-09-14
    • US850511
    • 1997-05-02
    • David ReesJames LutleySandeep Pant
    • David ReesJames LutleySandeep Pant
    • H01L27/02H02H4/00
    • H01L27/0248
    • An electrostatic discharge (ESD) protection circuit for an output transistor coupled to an I/O pin of an integrated circuit, including a logic circuit having at least one data input, a tristate enable input, and an tristate output coupled to a gate node of the output transistor wherein the tristate output is placed in a high impedance state in response to the tristate enable input. The ESD protection circuit also includes a tristate enable circuit which drives the tristate enable input according to the presence or absence of an ESD event on the I/O pin. During normal operation, the tristate enable circuit applies a first logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a low impedance state, and during an ESD event on the I/O pin, the tristate enable circuit applies a second logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a high impedance state.
    • 耦合到集成电路的I / O引脚的输出晶体管的静电放电(ESD)保护电路,包括具有至少一个数据输入的逻辑电路,三态使能输入和耦合到栅极节点的三态输出 输出晶体管,其中三态输出响应于三态使能输入而处于高阻抗状态。 ESD保护电路还包括三态使能电路,根据I / O引脚上存在或不存在ESD事件来驱动三态使能输入。 在正常操作期间,三态使能电路将第一逻辑电平施加到三态使能输入,使得逻辑电路的三态输出处于低阻态,并且在I / O引脚的ESD事件期间,三态使能 电路将第二逻辑电平施加到三态使能输入,使得逻辑电路的三态输出置于高阻抗状态。
    • 2. 发明授权
    • Reduced output swing with p-channel pullup diode connected
    • 降低输出摆幅,连接p沟道上拉二极管
    • US5781034A
    • 1998-07-14
    • US680288
    • 1996-07-11
    • David ReesSandeep Pant
    • David ReesSandeep Pant
    • H03K19/017H03K19/094H03K19/0185H03K19/0948
    • H03K19/09429H03K19/01721
    • An output buffer having a reduced-swing output includes a p-channel pullup transistor as the primary pullup device. A biasing circuit is provided so as to bias the gate terminal of the pullup p-channel transistor to a predetermined level. The predetermined level is effective to cause the p-channel pullup transistor to shut off when the output of the buffer reaches a reduced magnitude output level (V.sub.OH). In the disclosed embodiment, the biasing circuit includes an n-channel transistor connected between the gate and drain terminals of the p-channel pullup transistor. The biasing circuit also includes a p-channel transistor having a source terminal connected to V.sub.cc, and a drain terminal connected to the gate of the pullup transistor. When the output of the buffer is desired to be in a logic high state, both of the biasing transistors are "ON." The voltage applied to the gate of the pullup transistor is, in effect, the result of the voltage divider effect between the "ON" resistances of the two biasing transistors. These transistors divide the voltage between V.sub.cc and the voltage on the drain of the pullup transistor. A third p-channel transistor is provided, and which has a source terminal connected to V.sub.cc, and a drain terminal connected to the gate of the p-channel pullup transistor. This transistor is provided to turn the pullup transistor completely "OFF" in predetermined situations, such as when a pulldown circuit is to be activated, or when the buffer is to be tri-stated.
    • 具有减小摆幅输出的输出缓冲器包括作为主上拉装置的p沟道上拉晶体管。 提供偏置电路以将上拉p沟道晶体管的栅极端子偏置到预定水平。 当缓冲器的输出达到降低的幅度输出电平(VOH)时,预定电平有效地使p沟道上拉晶体管截止。 在所公开的实施例中,偏置电路包括连接在p沟道上拉晶体管的栅极和漏极端子之间的n沟道晶体管。 偏置电路还包括具有连接到Vcc的源极端子和连接到上拉晶体管的栅极的漏极端子的p沟道晶体管。 当希望缓冲器的输出处于逻辑高电平状态时,两个偏置晶体管都为“导通”。 施加到上拉晶体管的栅极的电压实际上是两个偏置晶体管的“导通”电阻之间的分压器效应的结果。 这些晶体管将Vcc之间的电压和上拉晶体管的漏极上的电压分开。 提供第三p沟道晶体管,其源极端子连接到Vcc,漏极端子连接到p沟道上拉晶体管的栅极。 该晶体管被提供以在预定的情况下,例如当下拉电路被激活时,或者当缓冲器被三态化时,将上拉晶体管完全“断开”。
    • 7. 发明授权
    • Option decoding with on-chip electrical fuses
    • 带片上电子保险丝的选件解码
    • US5821770A
    • 1998-10-13
    • US640032
    • 1996-04-30
    • David Rees
    • David Rees
    • H03K19/173H01H85/02
    • H03K19/1733
    • A method for varying the type of function selected on a chip (for example, after completion of manufacturing) may include the steps of providing predetermined fuse arrangements which individually or in combination correspond to each type of function on the chip and providing disable control lines having fuses to each of the predetermined fuse arrangements. When one of the types of circuits is selected, the predetermined fuse arrangement individually or in combination corresponding to that selected type of function is blown. The blowing of fuses may change the functionality of the chip directly or may perform a complex procedure such as controlling a portion of a decoding scheme which may radically change the function of the chip. To prevent further blowing of predetermined fuse arrangements, the fuses in disable control lines to each of the predetermined fuse arrangements may be blown, eliminating further selection of types of function.
    • 用于改变在芯片上选择的功能类型(例如,在制造完成之后)的方法可以包括以下步骤:提供单独地或组合地对应于芯片上的每种功能的预定熔丝装置,并提供具有 保险丝到每个预定的保险丝装置。 当选择其中一种类型的电路时,单独地或组合地对应于所选择的功能类型的预定熔丝装置被吹制。 保险丝的熔化可以直接改变芯片的功能,或者可以执行复杂的过程,例如控制可以从根本上改变芯片的功能的解码方案的一部分。 为了防止进一步吹送预定的保险丝装置,可以吹灭对每个预定的保险丝装置的禁止控制线路中的保险丝,从而消除了功能类型的进一步选择。