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1. 发明授权

US6049242A Voltage reference source for an overvoltage-tolerant bus interface 失效
标题翻译：用于过压公差总线接口的参考电压源
公开(公告)号：US6049242A
公开(公告)日：2000-04-11
申请号：US949861
申请日：1997-10-14
申请人： James Lutley , Sandeep Pant
发明人： James Lutley , Sandeep Pant
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315
摘要： The invention relates to a voltage reference source used to control an overvoltage tolerant input/output buffer for a mixed voltage bus system. The voltage source comprises a voltage tracking circuit having a first input receiving a variable voltage, and a second input receiving a reference voltage, the voltage tracking circuit being adapted to generate an output voltage in response to the difference between the variable voltage and the reference voltage, wherein where the variable voltage is less than the reference voltage, the output voltage is held at substantially zero volts. When the variable voltage exceeds the reference voltage, the output tracks the voltage at the variable voltage input.
摘要翻译：本发明涉及用于控制用于混合电压总线系统的过电压容限输入/输出缓冲器的电压参考源。电压源包括具有接收可变电压的第一输入端的电压跟踪电路和接收参考电压的第二输入端，所述电压跟踪电路适于响应于可变电压和参考电压之间的差而产生输出电压其中，在可变电压小于参考电压的情况下，输出电压保持在基本为零伏特。当可变电压超过参考电压时，输出跟踪可变电压输入端的电压。

2. 发明授权

US07573691B2 Electrical over stress robustness 有权
标题翻译：电应力鲁棒性强
公开(公告)号：US07573691B2
公开(公告)日：2009-08-11
申请号：US10821836
申请日：2004-04-12
申请人： Sandeep Pant , Gary H. Weiss , David W. Thompson , Yehuda Smooha
发明人： Sandeep Pant , Gary H. Weiss , David W. Thompson , Yehuda Smooha
IPC分类号： H02H3/22
CPC分类号： H01L27/0285
摘要： Protection is provided against electrical surges resulting from Electrical Over Stress conditions, e.g., when interfacing circuits with powered connections. An EOS shunt is activated for as long as the EOS condition exists. EOS protection using an EOS shunt in accordance with the principles of the present invention remains activated by a voltage threshold trigger as long as necessary. In a disclosed embodiment, an EOS shunt includes a voltage threshold detector that detects a voltage on a power bus with respect to a ground rail exceeding a predetermined amount, e.g., 5 volts in a device powered at 3.3 volts. During the EOS event, a path between power and ground comprising a transistor is turned on.
摘要翻译：提供了防止由电过压条件引起的电涌，例如当与电源连接相连的电路时。只要EOS条件存在，EOS分流器就被激活。根据本发明的原理使用EOS分流器的EOS保护由需要的电压阈值触发保持激活。在公开的实施例中，EOS分流器包括电压阈值检测器，该电压阈值检测器相对于超过预定量的接地轨，例如在以3.3V供电的设备中检测5伏特的电力总线上的电压。在EOS事件期间，包括晶体管的电源和地之间的路径导通。

3. 发明授权

US5953190A ESD protection circuit for I/O buffers 失效
标题翻译：用于I / O缓冲器的ESD保护电路
公开(公告)号：US5953190A
公开(公告)日：1999-09-14
申请号：US850511
申请日：1997-05-02
申请人： David Rees , James Lutley , Sandeep Pant
发明人： David Rees , James Lutley , Sandeep Pant
IPC分类号： H01L27/02 , H02H4/00
CPC分类号： H01L27/0248
摘要： An electrostatic discharge (ESD) protection circuit for an output transistor coupled to an I/O pin of an integrated circuit, including a logic circuit having at least one data input, a tristate enable input, and an tristate output coupled to a gate node of the output transistor wherein the tristate output is placed in a high impedance state in response to the tristate enable input. The ESD protection circuit also includes a tristate enable circuit which drives the tristate enable input according to the presence or absence of an ESD event on the I/O pin. During normal operation, the tristate enable circuit applies a first logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a low impedance state, and during an ESD event on the I/O pin, the tristate enable circuit applies a second logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a high impedance state.
摘要翻译：耦合到集成电路的I / O引脚的输出晶体管的静电放电（ESD）保护电路，包括具有至少一个数据输入的逻辑电路，三态使能输入和耦合到栅极节点的三态输出输出晶体管，其中三态输出响应于三态使能输入而处于高阻抗状态。 ESD保护电路还包括三态使能电路，根据I / O引脚上存在或不存在ESD事件来驱动三态使能输入。在正常操作期间，三态使能电路将第一逻辑电平施加到三态使能输入，使得逻辑电路的三态输出处于低阻态，并且在I / O引脚的ESD事件期间，三态使能电路将第二逻辑电平施加到三态使能输入，使得逻辑电路的三态输出置于高阻抗状态。

4. 发明申请

US20050225912A1 Electrical over stress robustness 有权
标题翻译：电应力鲁棒性强
公开(公告)号：US20050225912A1
公开(公告)日：2005-10-13
申请号：US10821836
申请日：2004-04-12
申请人： Sandeep Pant , Gary Weiss , David Thompson , Yehuda Smooha
发明人： Sandeep Pant , Gary Weiss , David Thompson , Yehuda Smooha
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0285
摘要： Protection is provided against electrical surges resulting from Electrical Over Stress conditions, e.g., when interfacing circuits with powered connections. An EOS shunt is activated for as long as the EOS condition exists. EOS protection using an EOS shunt in accordance with the principles of the present invention remains activated by a voltage threshold trigger as long as necessary. In a disclosed embodiment, an EOS shunt includes a voltage threshold detector that detects a voltage on a power bus with respect to a ground rail exceeding a predetermined amount, e.g., 5 volts in a device powered at 3.3 volts. During the EOS event, a path between power and ground comprising a transistor is turned on.
摘要翻译：提供了防止由电过压条件引起的电涌，例如当与电源连接相连的电路时。只要EOS条件存在，EOS分流器就被激活。根据本发明的原理使用EOS分流器的EOS保护由需要的电压阈值触发保持激活。在公开的实施例中，EOS分流器包括电压阈值检测器，该电压阈值检测器相对于超过预定量的接地轨，例如在以3.3V供电的设备中检测5伏特的电力总线上的电压。在EOS事件期间，包括晶体管的电源和地之间的路径导通。

5. 发明授权

US06265931B1 Voltage reference source for an overvoltage-tolerant bus interface 有权
标题翻译：用于过压公差总线接口的参考电压源
公开(公告)号：US06265931B1
公开(公告)日：2001-07-24
申请号：US09544962
申请日：2000-04-07
申请人： James Lutley , Sandeep Pant
发明人： James Lutley , Sandeep Pant
IPC分类号： H02J338
CPC分类号： H03K19/00315
摘要： The invention relates to a voltage reference source used to control an overvoltage tolerant input/output buffer for a mixed voltage bus system. The voltage source comprises a voltage tracking circuit having a first input receiving a variable voltage. and a second input receiving a reference voltage. the voltage tracking circuit being adapted to generate an output voltage in response to the difference between the variable voltage and the reference voltage. wherein where the variable voltage is less than the reference voltage. the output voltage is held at substantially zero volts. When the variable voltage exceeds the reference voltage. the output tracks the voltage at the variable voltage input.
摘要翻译：本发明涉及用于控制用于混合电压总线系统的过电压容限输入/输出缓冲器的电压参考源。电压源包括具有接收可变电压的第一输入的电压跟踪电路。以及接收参考电压的第二输入。电压跟踪电路适于响应于可变电压和参考电压之间的差异而产生输出电压。其中所述可变电压小于所述参考电压。输出电压保持在大致零伏特。当可变电压超过参考电压时。输出跟踪可变电压输入端的电压。

6. 发明授权

US6091271A Frequency doubling method and apparatus 失效
标题翻译：倍频方法和装置
公开(公告)号：US6091271A
公开(公告)日：2000-07-18
申请号：US107481
申请日：1998-06-30
申请人： Sandeep Pant , Scott A. Segan
发明人： Sandeep Pant , Scott A. Segan
IPC分类号： H03K5/00 , H03B19/00
CPC分类号： H03K5/00006
摘要： The frequency doubling circuit according to the present invention includes first and second pulse generating circuits generating first and second pulse trains based on a periodic input signal. The second pulse train is out of phase with the first pulse train, and a combining circuit combines the first and second pulse trains to generate a periodic output signal having twice the frequency of the periodic input signal. Both the first and second pulse generating circuits include first and second charge storage devices, with the second charge storage device having half the storage capacity of the first charge storage device.
摘要翻译：根据本发明的倍频电路包括基于周期性输入信号产生第一和第二脉冲串的第一和第二脉冲发生电路。第二脉冲串与第一脉冲序列不同相，并且组合电路组合第一和第二脉冲串以产生具有周期性输入信号频率的两倍的周期性输出信号。第一和第二脉冲发生电路都包括第一和第二电荷存储装置，其中第二电荷存储装置具有第一电荷存储装置的一半存储容量。

7. 发明授权

US5914844A Overvoltage-tolerant input-output buffers having a switch configured to isolate a pull up transistor from a voltage supply 失效
标题翻译：具有被配置为将上拉晶体管与电压源隔离的开关的过电压容忍输入输出缓冲器
公开(公告)号：US5914844A
公开(公告)日：1999-06-22
申请号：US949863
申请日：1997-10-14
申请人： James Lutley , Sandeep Pant
发明人： James Lutley , Sandeep Pant
IPC分类号： H03K19/003 , H02H3/22
CPC分类号： H03K19/00315
摘要： The invention relates to a mixed voltage bus system and in particular, interfaces between a number of integrated circuits and a bus where some of the integrated circuits operate at one logic level and others operate at a different logic level. An overvoltage tolerant interface for a semiconductor integrated device particulary useful in such a system may contain a pad, a pull-up transistor coupled to the pad, a voltage supply having an operating voltage, and an isolation switch operative to isolate the pull-up transistor from the voltage supply when a voltage at the pad exceeds the operating voltage of the voltage supply.
摘要翻译：本发明涉及一种混合电压总线系统，特别是多个集成电路和总线之间的接口，其中一些集成电路在一个逻辑电平上工作，而其它集成电路在不同的逻辑电平下工作。用于这种系统中特别有用的半导体集成器件的过电压容限接口可以包含焊盘，耦合到焊盘的上拉晶体管，具有工作电压的电压源，以及用于隔离上拉晶体管的隔离开关当焊盘上的电压超过电源的工作电压时，从电源供应。

8. 发明授权

US5781034A Reduced output swing with p-channel pullup diode connected 失效
标题翻译：降低输出摆幅，连接p沟道上拉二极管
公开(公告)号：US5781034A
公开(公告)日：1998-07-14
申请号：US680288
申请日：1996-07-11
申请人： David Rees , Sandeep Pant
发明人： David Rees , Sandeep Pant
IPC分类号： H03K19/017 , H03K19/094 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/09429 , H03K19/01721
摘要： An output buffer having a reduced-swing output includes a p-channel pullup transistor as the primary pullup device. A biasing circuit is provided so as to bias the gate terminal of the pullup p-channel transistor to a predetermined level. The predetermined level is effective to cause the p-channel pullup transistor to shut off when the output of the buffer reaches a reduced magnitude output level (V.sub.OH). In the disclosed embodiment, the biasing circuit includes an n-channel transistor connected between the gate and drain terminals of the p-channel pullup transistor. The biasing circuit also includes a p-channel transistor having a source terminal connected to V.sub.cc, and a drain terminal connected to the gate of the pullup transistor. When the output of the buffer is desired to be in a logic high state, both of the biasing transistors are "ON." The voltage applied to the gate of the pullup transistor is, in effect, the result of the voltage divider effect between the "ON" resistances of the two biasing transistors. These transistors divide the voltage between V.sub.cc and the voltage on the drain of the pullup transistor. A third p-channel transistor is provided, and which has a source terminal connected to V.sub.cc, and a drain terminal connected to the gate of the p-channel pullup transistor. This transistor is provided to turn the pullup transistor completely "OFF" in predetermined situations, such as when a pulldown circuit is to be activated, or when the buffer is to be tri-stated.
摘要翻译：具有减小摆幅输出的输出缓冲器包括作为主上拉装置的p沟道上拉晶体管。提供偏置电路以将上拉p沟道晶体管的栅极端子偏置到预定水平。当缓冲器的输出达到降低的幅度输出电平（VOH）时，预定电平有效地使p沟道上拉晶体管截止。在所公开的实施例中，偏置电路包括连接在p沟道上拉晶体管的栅极和漏极端子之间的n沟道晶体管。偏置电路还包括具有连接到Vcc的源极端子和连接到上拉晶体管的栅极的漏极端子的p沟道晶体管。当希望缓冲器的输出处于逻辑高电平状态时，两个偏置晶体管都为“导通”。施加到上拉晶体管的栅极的电压实际上是两个偏置晶体管的“导通”电阻之间的分压器效应的结果。这些晶体管将Vcc之间的电压和上拉晶体管的漏极上的电压分开。提供第三p沟道晶体管，其源极端子连接到Vcc，漏极端子连接到p沟道上拉晶体管的栅极。该晶体管被提供以在预定的情况下，例如当下拉电路被激活时，或者当缓冲器被三态化时，将上拉晶体管完全“断开”。

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