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1. 发明授权

US07955919B2 Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes 有权
标题翻译：用于高K栅极介质和适用于Si，SiGe和应变硅方案的小栅极到栅极空间的无间隔晶体管集成方案
公开(公告)号：US07955919B2
公开(公告)日：2011-06-07
申请号：US11960554
申请日：2007-12-19
申请人： David Pritchard , Hemanshu Bhatt , David T. Price
发明人： David Pritchard , Hemanshu Bhatt , David T. Price
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/823807 , H01L21/823828 , H01L29/4958 , H01L29/665 , H01L29/66606
摘要： A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.
摘要翻译：晶体管积分过程提供了用于形成栅极电极和栅极电介质层的镶嵌方法。在栅电极形成之前沉积层间绝缘膜，以避免由相邻栅极呈现的苛刻的间隙填充要求。在层间电介质膜中形成沟槽，随后在沟槽中沉积栅极材料。该过程避免了由高热循环引起的对高k栅极电介质层的损坏的可能性，并且还减少或消除填充相邻栅极之间的间隙的电介质层中空隙的有问题的形成。

2. 发明申请

US20070259518A1 Method and apparatus for diverting void diffusion in integrated circuit conductors 有权
标题翻译：用于在集成电路导体中转移空穴扩散的方法和装置
公开(公告)号：US20070259518A1
公开(公告)日：2007-11-08
申请号：US11323398
申请日：2005-12-29
申请人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
发明人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
IPC分类号： H01L29/06 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/7682 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
摘要翻译：在集成电路中转移空穴扩散的方法包括以下步骤：在集成电路的第一导电层中形成具有边界的电导体，在电介质层的边界内在第一导电层和第二导电层，并且在电导体的通孔和边界之间形成槽，用于将电导体中的空隙扩散转移离开通孔。

3. 发明申请

US20080102583A1 SPACER-LESS TRANSISTOR INTEGRATION SCHEME FOR HIGH-K GATE DIELECTRICS AND SMALL GATE-TO-GATE SPACES APPLICABLE TO SI, SIGE AND STRAINED SILICON SCHEMES 有权
标题翻译：适用于SI，信号和应变硅计划的高K栅介质和小门到门空间的间隔不足的晶体管集成方案
公开(公告)号：US20080102583A1
公开(公告)日：2008-05-01
申请号：US11960554
申请日：2007-12-19
申请人： David Pritchard , Hemanshu Bhatt , David Price
发明人： David Pritchard , Hemanshu Bhatt , David Price
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/823807 , H01L21/823828 , H01L29/4958 , H01L29/665 , H01L29/66606
摘要： A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.
摘要翻译：晶体管积分过程提供了用于形成栅极电极和栅极电介质层的镶嵌方法。在栅电极形成之前沉积层间绝缘膜，以避免由相邻栅极呈现的苛刻的间隙填充要求。在层间电介质膜中形成沟槽，随后在沟槽中沉积栅极材料。该过程避免了由高热循环引起的对高k栅极电介质层的损坏的可能性，并且还减少或消除填充相邻栅极之间的间隙的电介质层中空隙的有问题的形成。

4. 发明申请

US20060088990A1 Local interconnect manufacturing process 有权
标题翻译：本地互连制造工艺
公开(公告)号：US20060088990A1
公开(公告)日：2006-04-27
申请号：US10971961
申请日：2004-10-22
申请人： Santosh Menon , Hemanshu Bhatt , David Pritchard
发明人： Santosh Menon , Hemanshu Bhatt , David Pritchard
IPC分类号： H01L21/44
CPC分类号： H01L21/76895
摘要： The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.
摘要翻译：本发明涉及一种制造局部互连的方法。所公开的方法包括在晶体管的两个电触点之上的ILD中形成两个分离的空腔。第一腔向下延伸到下面的蚀刻停止层。然后用保护层填充第一个空腔。然后，第二腔形成在第一腔附近并向下延伸以露出下面的蚀刻停止层。去除保护层以形成包括第一和第二空腔的扩展空腔，其暴露扩展空腔中的下面的蚀刻停止层。扩散腔中的蚀刻停止材料也被去除以暴露下面的栅极接触并暴露源极或漏极接触中的一个。然后将栅极触点与暴露的源极或漏极触点中的一个电连接以形成局部互连。

5. 发明申请

US20070155160A1 Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design 有权
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法和装置
公开(公告)号：US20070155160A1
公开(公告)日：2007-07-05
申请号：US11323400
申请日：2005-12-29
申请人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
发明人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：用于在集成电路设计中将空隙扩散转向远离通孔的方法和装置包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二电导体之间形成通孔集成电路设计的导电层，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

6. 发明申请

US20050191812A1 Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe strained silicon schemes 审中-公开
标题翻译：用于高k栅极电介质和适用于Si，SiGe应变硅方案的小栅极到栅极空间的无间隔晶体管集成方案
公开(公告)号：US20050191812A1
公开(公告)日：2005-09-01
申请号：US10791337
申请日：2004-03-01
申请人： David Pritchard , Hemanshu Bhatt , David Price
发明人： David Pritchard , Hemanshu Bhatt , David Price
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/51
CPC分类号： H01L29/517 , H01L21/823807 , H01L21/823828 , H01L29/4958 , H01L29/665 , H01L29/66606
摘要： A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.
摘要翻译：晶体管积分过程提供了用于形成栅极电极和栅极电介质层的镶嵌方法。在栅电极形成之前沉积层间绝缘膜，以避免由相邻栅极呈现的苛刻的间隙填充要求。在层间电介质膜中形成沟槽，随后在沟槽中沉积栅极材料。该过程避免了由高热循环引起的对高k栅极电介质层的损坏的可能性，并且还减少或消除填充相邻栅极之间的间隙的电介质层中空隙的有问题的形成。

7. 发明授权

US08552587B2 Power conversion for distributed DC source array 有权
标题翻译：分布式直流电源阵列的功率转换
公开(公告)号：US08552587B2
公开(公告)日：2013-10-08
申请号：US12840130
申请日：2010-07-20
申请人： Sunit Tyagi , Hemanshu Bhatt
发明人： Sunit Tyagi , Hemanshu Bhatt
IPC分类号： H02J1/10
CPC分类号： H02M7/537 , H02J3/383 , H02M7/493 , H02M2007/4815 , Y02B70/1441 , Y02E10/563 , Y10T307/50 , Y10T307/658 , Y10T307/713
摘要： Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.
摘要翻译：公开了将直流电转换为交流电力的实施例。例如，一个公开的实施例提供了一种功率转换系统，其包括多个直流（DC）电源，多个以并联装置彼此连接的功率输出电路，每个功率输出电路连接到相应的直流电力源极，用于从相应的直流电源接收电力并选择性地放电从相应的直流电源接收的功率;功率组合器，被配置为组合从多个功率输出电路接收的功率以形成组合的功率信号;输出级，被配置为将组合的功率信号转换为AC信号或DC信号，以及与每个电源插座电路和功率组合器电连接的控制器，以通过功率转换器来控制功率的输出。

8. 发明授权

US07205673B1 Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing 有权
标题翻译：在Cu / Low-k BEOL处理过程中，通过掺杂在焊盘中使用的铝来减少或消除后引线键合模具中的IMC裂纹
公开(公告)号：US07205673B1
公开(公告)日：2007-04-17
申请号：US11283044
申请日：2005-11-18
申请人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao
发明人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53219 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05147 , H01L2224/05624 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.
摘要翻译：一种接合焊盘结构，其包括铝接合焊盘，其包括一个或多个掺杂剂，其有效地将IMC的生长控制到标称电平，尽管晶片中存在高拉伸应力。例如，铝可以掺杂1-2原子％的Mg。或者，可以使用Pd或Si，或者可以使用诸如Cu或Si的元素作为掺杂剂，以便降低晶片中的整体拉伸应力。这可以控制IMC的异常生长，从而阻止IMC裂纹形成。可以使用掺杂剂的组合来控制拉伸应力并且还稍微改变金 - 铝界面，从而实现均匀和薄的IMC形成。这倾向于减少或消除否则在引线键合转移时会发生的任何空隙或裂纹。

9. 发明申请

US20060063338A1 Shallow trench isolation depth extension using oxygen implantation 审中-公开
标题翻译：浅沟槽隔离深度延长使用氧气注入
公开(公告)号：US20060063338A1
公开(公告)日：2006-03-23
申请号：US10946030
申请日：2004-09-20
申请人： Santosh Menon , Hemanshu Bhatt
发明人： Santosh Menon , Hemanshu Bhatt
IPC分类号： H01L21/336
CPC分类号： H01L21/26533 , H01L21/02118 , H01L21/02137 , H01L21/02164 , H01L21/3122 , H01L21/3124 , H01L21/76224 , H01L21/76237 , H01L21/76283 , H01L29/78609
摘要： The present invention is directed to structures and fabrication methods used to construct an improved shallow trench isolation structure are disclosed. The method involves providing a semiconductor substrate having a shallow isolation trench. The trench is implanted with oxygen to form an implanted region at the bottom of the trench. The trench is filled with dielectric materials. The substrate is planarized and then annealed to complete formation of the isolation structure. A structure having an improved isolation structure is also disclosed. The structure comprises a substrate configured to include a shallow trench that is filled with dielectric material. An insulating extension is formed by oxygen implantation of the regions underlying the shallow trench.
摘要翻译：本发明涉及用于构造改进的浅沟槽隔离结构的结构和制造方法。该方法包括提供具有浅隔离沟槽的半导体衬底。沟槽被注入氧气以在沟槽的底部形成注入区域。沟槽填充介电材料。将基材平面化，然后退火以完成隔离结构的形成。还公开了具有改进的隔离结构的结构。该结构包括被配置为包括填充有电介质材料的浅沟槽的衬底。通过浅沟槽下面的区域的氧注入形成绝缘延伸。

10. 发明申请

US20070254448A1 Integrated circuit with inductor having horizontal magnetic flux lines 有权
公开(公告)号：US20070254448A1
公开(公告)日：2007-11-01
申请号：US11811519
申请日：2007-06-11
申请人： Hemanshu Bhatt , Jan Fure , Derryl Allman
发明人： Hemanshu Bhatt , Jan Fure , Derryl Allman
IPC分类号： H01L21/00
CPC分类号： H01L28/10 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.

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