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1. 发明申请

US20050242843A1 Differential current mode phase/frequency detector circuit 失效
标题翻译：差分电流模式相位/频率检测电路
公开(公告)号：US20050242843A1
公开(公告)日：2005-11-03
申请号：US10833397
申请日：2004-04-28
申请人： David Meltzer , Muralikumar Padaparambil , Tat Wu
发明人： David Meltzer , Muralikumar Padaparambil , Tat Wu
IPC分类号： H03K5/26 , H03D13/00 , H03L7/089 , H03K19/003
CPC分类号： H03D13/004
摘要： A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.
摘要翻译：全差分相位和频率检测器利用多功能差分逻辑门来实现差分和门操作，并提供完全差分D触发器。多功能差分逻辑门有四个输入，可以分为两对真和补两个信号。通过选择性地将输入重新分配给不同的信号对，可以使差分逻辑门提供同时的与/或非逻辑运算或同时的OR / NOR逻辑运算之一。差分D-触发器按照主/从配置实现，并且响应于输入时钟信号，输入复位输入和输入数据信号的真实和补码形式，并且还提供输出的真实和补充形式信号。相位和频率检测器中的所有组件都以CML电路配置为例。

2. 发明申请

US20050242859A1 Differential master/slave CML latch 失效
标题翻译：差分主/从CML锁存器
公开(公告)号：US20050242859A1
公开(公告)日：2005-11-03
申请号：US10833605
申请日：2004-04-28
申请人： David Meltzer , Muralikumar Padaparambil , Tat Wu
发明人： David Meltzer , Muralikumar Padaparambil , Tat Wu
IPC分类号： H03K3/3562 , H03K3/0233 , H03K3/037 , H03K3/356 , H03K5/26 , H03K19/003 , H03L7/089
CPC分类号： H03K3/356139 , H03K3/3562
摘要： A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.
摘要翻译：全差分相位和频率检测器利用多功能差分逻辑门来实现差分和门操作，并提供完全差分D触发器。多功能差分逻辑门有四个输入，可以分为两对真和补两个信号。通过选择性地将输入重新分配给不同的信号对，可以使差分逻辑门提供同时的与/或非逻辑运算或同时的OR / NOR逻辑运算之一。差分D-触发器按照主/从配置实现，并且响应于输入时钟信号，输入复位输入和输入数据信号的真实和补码形式，并且还提供输出的真实和补充形式信号。相位和频率检测器中的所有组件都以CML电路配置为例。

3. 发明申请

US20050242842A1 Multi-function differential logic gate 失效
标题翻译：多功能差分逻辑门
公开(公告)号：US20050242842A1
公开(公告)日：2005-11-03
申请号：US10833398
申请日：2004-04-28
申请人： David Meltzer , Muralikumar Padaparambil , Tat Wu
发明人： David Meltzer , Muralikumar Padaparambil , Tat Wu
IPC分类号： H03K3/3562 , H03D13/00 , H03K3/356 , H03K19/094 , H03K19/096 , H03K19/20 , H03L7/085 , H03L7/089
CPC分类号： H03K3/356043 , H03D13/00 , H03L7/085
摘要： A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.
摘要翻译：全差分相位和频率检测器利用多功能差分逻辑门来实现差分和门操作，并提供完全差分D触发器。多功能差分逻辑门有四个输入，可以分为两对真和补两个信号。通过选择性地将输入重新分配给不同的信号对，可以使差分逻辑门提供同时的与/或非逻辑运算或同时的OR / NOR逻辑运算之一。差分D-触发器按照主/从配置实现，并且响应于输入时钟信号，输入复位输入和输入数据信号的真实和补码形式，并且还提供输出的真实和补充形式信号。相位和频率检测器中的所有组件都以CML电路配置为例。

4. 发明申请

US20060132209A1 CMOS master/slave flip-flop with integrated multiplexor 失效
标题翻译：具有集成多路复用器的CMOS主/从触发器
公开(公告)号：US20060132209A1
公开(公告)日：2006-06-22
申请号：US11016430
申请日：2004-12-17
申请人： David Meltzer , Muralikumar Padaparambil
发明人： David Meltzer , Muralikumar Padaparambil
IPC分类号： H03K3/289
CPC分类号： H03K3/356139
摘要： A CML master-slave latch incorporates logic into its master latching circuitry to incorporate a multiplexing function into the flip-flop. The multiplexing logic makes use of the pull-up loads and current source of the master latching circuitry. In this manner the pull-up loads and current source typically required for a stand-alone multiplexor are eliminated. Subsequently, the size of the present hybrid master-slave latch is smaller and consumes less power than a traditional combination of an independent multiplexor and master-slave latch. Since the master latching circuitry feeds only into the slave latching circuitry, the pull-up loads and the current sources of the master latching circuitry and slave latching circuitry may be optimized separately for achieving faster performance or less power consumption.
摘要翻译： CML主从锁存器将逻辑并入其主锁存电路，以将多路复用功能并入到触发器中。复用逻辑利用主锁存电路的上拉负载和电流源。以这种方式，消除了独立复用器通常需要的上拉负载和电流源。随后，当前的混合主 - 从锁存器的大小比独立多路复用器和主 - 从锁存器的传统组合消耗更少的功率。由于主锁存电路仅馈入从锁存电路，因此可以单独优化主锁存电路和从锁存电路的上拉负载和电流源，以实现更快的性能或更低的功耗。

5. 发明申请

US20070168589A1 Circuits and methods for high speed and low power data serialization 失效
标题翻译：用于高速和低功耗数据串行化的电路和方法
公开(公告)号：US20070168589A1
公开(公告)日：2007-07-19
申请号：US11333715
申请日：2006-01-17
申请人： Muralikumar Padaparambil
发明人： Muralikumar Padaparambil
IPC分类号： G06F13/38
CPC分类号： H03M9/00
摘要： Circuits and methods convert parallel data into a serial data stream. A serializer according to the present invention generally includes a high speed section and a low speed section. The high speed section generally comprises a tree-based serializer configured to serialize an N-bit parallel data stream, where N is a power of two. The low speed section generally includes a data bank configured to load one or more samples of an M-bit parallel input stream, and a multiplexer configured to produce the N-bit parallel data stream from the data bank. The present invention advantageously provides high speed and relatively low power serialization of M-bit parallel data streams where M is not a power of two. In particular, the present invention advantageously provides high speed and relatively low power serialization of 10-bit parallel data streams.
摘要翻译：电路和方法将并行数据转换为串行数据流。根据本发明的串行器通常包括高速部分和低速部分。高速部分通常包括被配置为串行化N位并行数据流的基于树的串行器，其中N是2的幂。低速部分通常包括被配置为加载M位并行输入流的一个或多个采样的数据组，以及被配置为从数据库产生N位并行数据流的多路复用器。本发明有利地提供M位并行数据流的高速度和相对低功率的串行化，其中M不是2的幂。特别地，本发明有利地提供10位并行数据流的高速度和相对低功率的串行化。

6. 发明申请

US20060103557A1 LOW-POWER SERIALIZER WITH HALF-RATE CLOCKING AND METHOD 失效
标题翻译：具有高速率时钟的低功率串行器和方法
公开(公告)号：US20060103557A1
公开(公告)日：2006-05-18
申请号：US10990120
申请日：2004-11-16
申请人： Muralikumar Padaparambil
发明人： Muralikumar Padaparambil
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A serializer for multiplexing 2N data streams, each data stream having a frequency of f/(2N), N being a positive integer. The serializer comprises 2N-1 instances of a dual-edge multiplexer flip-flop circuit, N frequency domains including a first frequency domain having the frequency f/2N and a last frequency domain having a frequency f/2, and an output providing serialized data at frequency f clocked at half that rate. Thus, the highest clock signal frequency input into the serializer is f/2.
摘要翻译：一种串行器，用于多路复用2个N / N个数据流，每个数据流具有f /（2 N N）的频率，N是正整数。串行器包括双边多路复用器触发器电路的2个N 1个实例，N个频域包括具有频率f / 2 N的第一频域和具有频率f / 2的最后频域，以及以频率f以该速率的一半提供串行化数据的输出。因此，输入串行器的最高时钟信号频率为f / 2。

7. 发明申请

US20070013424A1 Differential dual-edge triggered multiplexer flip-flop and method 审中-公开
标题翻译：差分双边沿触发多路复用器触发器和方法
公开(公告)号：US20070013424A1
公开(公告)日：2007-01-18
申请号：US11184205
申请日：2005-07-18
申请人： Muralikumar Padaparambil
发明人： Muralikumar Padaparambil
IPC分类号： H03K3/00
CPC分类号： H03K3/356139 , H03K17/693
摘要： A differential dual-edge triggered multiplexer flip-flop configured and operated to capture a first data signal on one edge of the clock and a second data signal on the other clock edge. By so doing, the output data rate of such a flip-flop is twice that of the input data rate but clocked with half the frequency, as compared to a single-edge triggered flip-flop implementation. This reduction in clock frequency reduces power consumption, as compared to a conventional single-edge triggered flip-flop, for an identical throughput. Such a flip-flop includes two main latches that operate in complementary fashion, that is, when one is holding data, the other is providing data for sampling by the corresponding circuitry in the multiplexer of the flip-flop. In an alternate embodiment, two main latches have both data inputs tied together to accomplish the function of a regular dual-edge triggered flip-flop. In this case, a data signal is sampled and passed to the output of the multiplexer during every clock transition.
摘要翻译：配置和操作的差分双边沿触发多路复用器触发器捕获时钟的一个边缘上的第一数据信号，并在另一个时钟边沿捕获第二数据信号。通过这样做，与单边缘触发的触发器实现相比，这种触发器的输出数据速率是输入数据速率的两倍，但是以一半的频率计时。与传统的单边沿触发触发器相比，时钟频率的这种减少降低了功耗，达到相同的吞吐量。这样的触发器包括以互补方式操作的两个主锁存器，即当保持数据时，另一个主要锁存器提供用于由触发器的多路复用器中的相应电路进行采样的数据。在替代实施例中，两个主锁存器具有连接在一起的数据输入端以实现常规双边沿触发触发器的功能。在这种情况下，在每个时钟转换期间，数据信号被采样并传送到多路复用器的输出。

8. 发明申请

US20060104124A1 Dual-edge triggered multiplexer flip-flop and method 失效
标题翻译：双边沿触发多路复用器触发器和方法
公开(公告)号：US20060104124A1
公开(公告)日：2006-05-18
申请号：US10990119
申请日：2004-11-16
申请人： Muralikumar Padaparambil
发明人： Muralikumar Padaparambil
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/106 , H03M9/00
摘要： A dual edge multiplexing flip-flop comprises a first circuit block having a first data input, a first clock signal input, a supply voltage input, and a ground connection; a second circuit block having a second data input, a second clock signal input, a supply voltage input, and a ground connection. Each circuit block is coupled to a common output node. When a common clock signal is input into the clock signal inputs, each circuit block outputs a floating voltage during one half of each clock cycle and a voltage indicative of a corresponding data input signal during the other half of each clock cycle.
摘要翻译：双边缘多路复用触发器包括具有第一数据输入，第一时钟信号输入，电源电压输入和接地连接的第一电路块; 具有第二数据输入，第二时钟信号输入，电源电压输入和接地连接的第二电路块。每个电路块耦合到公共输出节点。当公共时钟信号被输入到时钟信号输入中时，每个电路块在每个时钟周期的一半期间输出浮置电压，并且在每个时钟周期的另一半期间输出表示对应的数据输入信号的电压。

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