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1. 发明授权

US07620876B2 Reducing false positives in configuration error detection for programmable devices 有权
标题翻译：减少可编程器件配置错误检测中的误报
公开(公告)号：US07620876B2
公开(公告)日：2009-11-17
申请号：US11407519
申请日：2006-04-19
申请人： David Lewis , Robert Blake , Richard G. Cliff , Srinivas T. Reddy
发明人： David Lewis , Robert Blake , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G06F11/1008 , G11C29/52
摘要： A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data indicates unused portions of the memory. Unused portions of the memory may correspond with configuration data for unused portions of a programmable device. Each bit of the sensitivity mask data may indicate the usage of one or more bits of the data from the memory. In response to the mask data, the masking unit sets data from the unused portions of the memory to values that do not change the result of the error detection computations. This prevents any errors in data from the unused portions of the memory from raising an error signal.
摘要翻译：设备通过使用掩蔽单元和灵敏度掩码数据来减少假阳性存储器错误检测，以从错误检测计算中排除存储器的未使用部分。一种设备包括一个错误检测单元，用于从存储器读取数据并验证数据完整性。灵敏度掩码数据指示存储器的未使用部分。存储器的未使用部分可以对应于可编程设备的未使用部分的配置数据。灵敏度掩码数据的每一位可以指示来自存储器的数据的一位或多位的使用。响应于掩模数据，掩蔽单元将来自存储器的未使用部分的数据设置为不改变错误检测计算结果的值。这防止来自存储器的未使用部分的数据中的任何错误引起错误信号。

2. 发明申请

US20110204919A1 Apparatus and methods for adjusting performance of programmable logic devices 有权
公开(公告)号：US20110204919A1
公开(公告)日：2011-08-25
申请号：US13098450
申请日：2011-04-30
申请人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
发明人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
IPC分类号： H03K19/177
CPC分类号： H03K19/17784 , H03K19/17788 , H03K19/17792
摘要： A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

3. 发明授权

US07936184B2 Apparatus and methods for adjusting performance of programmable logic devices 有权
标题翻译：用于调节可编程逻辑器件性能的装置和方法
公开(公告)号：US07936184B2
公开(公告)日：2011-05-03
申请号：US11361642
申请日：2006-02-24
申请人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
发明人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
IPC分类号： H01L25/00
CPC分类号： H03K19/17784 , H03K19/17788 , H03K19/17792
摘要： A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.
摘要翻译：可编程逻辑器件（PLD）至少包括两个区域。每个区域包括具有一组晶体管的电路。两个区域中的每一个具有对应的固定晶体管阈值电压，对应的固定晶体管体偏置和相应的固定电源电压。

4. 发明授权

US07236008B1 Multiple size memories in a programmable logic device 有权
标题翻译：可编程逻辑器件中的多个大小的存储器
公开(公告)号：US07236008B1
公开(公告)日：2007-06-26
申请号：US11611122
申请日：2006-12-14
申请人： Richard G. Cliff , Srinivas T. Reddy , Andy L. Lee , David Lewis
发明人： Richard G. Cliff , Srinivas T. Reddy , Andy L. Lee , David Lewis
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/17728
摘要： Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.
摘要翻译：提供具有多种尺寸的存储器的集成电路的电路，方法和装置。存储器可以是专用的嵌入式存储器，或者它们可以是使用逻辑元件或其他适当电路中的存储器或查找表形成的分布式存储器。用于分布式存储器的逻辑元件不需要的配置位也可以用于数据存储。这些各种存储器可以以不同的组合组合或以其他方式链接或链接在一起以形成不同大小的较大存储器。

5. 发明授权

US08198914B2 Apparatus and methods for adjusting performance of programmable logic devices 有权
标题翻译：用于调节可编程逻辑器件性能的装置和方法
公开(公告)号：US08198914B2
公开(公告)日：2012-06-12
申请号：US13098450
申请日：2011-04-30
申请人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
发明人： Andy L. Lee , Christopher F. Lane , Ketan H. Zaveri , Richard G. Cliff , Cameron R. McClintock , Srinivas T. Reddy , David Lewis
IPC分类号： H01L25/00
CPC分类号： H03K19/17784 , H03K19/17788 , H03K19/17792
摘要： A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.
摘要翻译：可编程逻辑器件（PLD）至少包括两个区域。每个区域包括具有一组晶体管的电路。两个区域中的每一个具有对应的固定晶体管阈值电压，对应的固定晶体管体偏置和相应的固定电源电压。

6. 发明授权

US06879183B2 Programmable logic device architectures with super-regions having logic regions and a memory region 有权
标题翻译：具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
公开(公告)号：US06879183B2
公开(公告)日：2005-04-12
申请号：US10260712
申请日：2002-09-27
申请人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
发明人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
摘要翻译：可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。每个逻辑区域包括可编程逻辑的多个子区域。每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源装置。

7. 发明授权

US06815981B2 Programmable logic array integrated circuit devices 失效
标题翻译：可编程逻辑阵列集成电路器件
公开(公告)号：US06815981B2
公开(公告)日：2004-11-09
申请号：US10361477
申请日：2003-02-06
申请人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
发明人： Richard G. Cliff , Srinivas T. Reddy , David Edward Jefferson , Rina Raman , L. Todd Cope , Christopher F. Lane , Joseph Huang , Francis B. Heile , Bruce B. Pedersen , David Wolk Mendel , Craig Schilling Lytle , Robert Richard Noel Bielby , Kerry Veenstra
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.
摘要翻译：可编程逻辑阵列集成电路器件包括以相交的行和列的二维阵列布置在器件上的可编程逻辑的多个区域。互连导体与每行和列相关联。与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。还提供了许多其他增强功能。

8. 发明授权

US06467017B1 Programmable logic device having embedded dual-port random access memory configurable as single-port memory 失效
标题翻译：具有可配置为单端口存储器的嵌入式双端口随机存取存储器的可编程逻辑器件
公开(公告)号：US06467017B1
公开(公告)日：2002-10-15
申请号：US09124649
申请日：1998-07-29
申请人： Tony K. Ngai , Rakesh H. Patel , Srinivas T. Reddy , Richard G. Cliff
发明人： Tony K. Ngai , Rakesh H. Patel , Srinivas T. Reddy , Richard G. Cliff
IPC分类号： G06F1200
CPC分类号： H03K19/1776 , G11C7/1075 , G11C2207/104 , H03K19/17736
摘要： A programmable logic device has embedded random access memory (“RAM”) that can function equally well in either single-port or dual-port operation. The RAM is dual-port RAM whose read address inputs and write address inputs are both connected to a conductor bus via two different sparsely populated programmable interconnection resources. The programmable interconnection resources are arranged so that each pair of corresponding read address and write address inputs can be connected to at least one conductor in common on the conductor bus, allowing the RAM to be configured to mimic a single-port RAM as read address signals and write address signals originating at remote components of the programmable logic device “think” they are being directed to the same address inputs.
摘要翻译：可编程逻辑器件具有嵌入式随机存取存储器（“RAM”），其可在单端口或双端口操作中同等功能。 RAM是双端口RAM，其读地址输入和写地址输入都通过两个不同的稀疏布置的可编程互连资源连接到导体总线。可编程互连资源被布置为使得每对相应的读取地址和写入地址输入可以在导体总线上共同连接到至少一个导体，从而允许RAM被配置为模拟单端口RAM作为读取地址信号并且写入源自可编程逻辑器件的远程组件的地址信号“认为”它们被引导到相同的地址输入。

9. 发明授权

US06392954B2 Dual port programmable logic device variable depth and width memory array 有权
标题翻译：双端口可编程逻辑器件可变深度和宽度存储器阵列
公开(公告)号：US06392954B2
公开(公告)日：2002-05-21
申请号：US09747191
申请日：2000-12-21
申请人： Srinivas T. Reddy , Christopher F. Lane , Manuel Mejia , Richard G. Cliff , Kerry Veenstra
发明人： Srinivas T. Reddy , Christopher F. Lane , Manuel Mejia , Richard G. Cliff , Kerry Veenstra
IPC分类号： G11C800
CPC分类号： G11C7/1006
摘要： A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.
摘要翻译：提供了双端口可编程逻辑器件存储器阵列。可选择大小的数据字可以并行写入阵列并从阵列中读取。使用写列解码器和数据选择逻辑将数据写入阵列。由写列解码器和数据选择逻辑处理的数据字的大小由模式选择信号控制。使用读列解码器和数据选择逻辑从数组中读取数据。由读列解码器和数据选择逻辑处理的数据字的大小也由模式选择信号控制。写列解码器和数据选择逻辑可以用于在一个选定位置将数据写入存储器阵列，同时读列解码器和数据选择逻辑用于在另一选定位置从阵列中读取数据。写入行地址解码器和读取行地址解码器分别用于在写入和读取期间独立地对存储器阵列中的存储单元的各行进行寻址。

10. 发明授权

US06335634B1 Circuitry and methods for internal interconnection of programmable logic devices 有权
标题翻译：可编程逻辑器件内部互连的电路和方法
公开(公告)号：US06335634B1
公开(公告)日：2002-01-01
申请号：US09577297
申请日：2000-05-22
申请人： Srinivas T. Reddy , Ketan Zaveri , Christopher F. Lane , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen , Manuel Mejia , Richard G. Cliff
发明人： Srinivas T. Reddy , Ketan Zaveri , Christopher F. Lane , Andy L. Lee , Cameron R. McClintock , Bruce B. Pedersen , Manuel Mejia , Richard G. Cliff
IPC分类号： G06F738
CPC分类号： H03K19/17736 , H03K19/17792
摘要： Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.
摘要翻译：提供了用于在可编程逻辑器件上选择性地互连逻辑的可编程互连组布置。互连组可以被编程为在设备上的各种导体之间路由信号，并且将信号从设备上的各种逻辑区域路由到各种导体。互连组提供路由灵活性和效率，而不需要使用过多的互连资源。

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