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1. 发明授权

US06169422A Apparatus and methods for high throughput self-timed domino circuits 失效
标题翻译：用于高通量自定时多米诺骨牌电路的装置和方法
公开(公告)号：US06169422A
公开(公告)日：2001-01-02
申请号：US09119032
申请日：1998-07-20
申请人： David L. Harris , William S. Coates
发明人： David L. Harris , William S. Coates
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： Asynchronous circuitry provides a domino circuit having short cycle times and zero overhead latency. The control circuit of a datapath circuit may utilize a completion signal from the datapath circuit to develop a request signal to the datapath circuit. The request signal may also be based on a request signal from a previous stage. Using the completion signal of a stage to develop the request signal for the same stage allows the circuitry to reduce the impact of constraints that are required for the asynchronous circuitry to operate. Similarly, using the request signal from a previous stage of the asynchronous circuitry to develop the request signal for a present stage also allows the circuitry to reduce the impact of constraints required to implement the asynchronous circuitry. These techniques allow the achievement of fast cycle times while maintaining zero overhead.
摘要翻译：异步电路提供具有短周期时间和零开销延迟的多米诺骨牌电路。数据路径电路的控制电路可以利用来自数据路径电路的完成信号来产生对数据路径电路的请求信号。请求信号也可以基于来自前一级的请求信号。使用级的完成信号来开发用于相同级的请求信号，使得电路可以减少异步电路运行所需的约束的影响。类似地，使用来自异步电路的前一级的请求信号来开发用于当前级的请求信号也允许电路减少实现异步电路所需的约束的影响。这些技术允许实现快速循环时间，同时保持零开销。

2. 发明授权

US07693925B2 Multiplicand shifting in a linear systolic array modular multiplier 失效
标题翻译：线性收缩阵列乘法器中的乘法运算
公开(公告)号：US07693925B2
公开(公告)日：2010-04-06
申请号：US11242573
申请日：2005-09-30
申请人： Sanu K. Mathew , David L. Harris , Ram Krishnamurthy
发明人： Sanu K. Mathew , David L. Harris , Ram Krishnamurthy
IPC分类号： G06F7/72
CPC分类号： G06F7/728 , G06F5/01
摘要： Embodiments of apparatuses and methods for multiplicand shifting in a linear systolic array modular multiplier are disclosed. In one embodiment, an apparatus includes two processing elements of a linear systolic array. One processing element includes multiplication logic, multiplicand shift logic, an adder, modulus logic, and modulus shift logic. The multiplication logic is to multiply a word of the multiplicand and a bit of the multiplier to generate a product. The multiplicand shift logic is to shift the word of the multiplicand. The adder is to add the product to a first running sum to generate a second running sum. The modulus logic is to conditionally add a word of a modulus and the second running sum. The modulus shift logic is to shift the word of the modulus. The next processing element includes logic to multiply the shifted word of the multiplicand and the next bit of the multiplier.
摘要翻译：公开了在线性收缩阵列模数乘法器中被乘数移位的装置和方法的实施例。在一个实施例中，装置包括线性收缩阵列的两个处理元件。一个处理元件包括乘法逻辑，被乘数移位逻辑，加法器，模数逻辑和模移位逻辑。乘法逻辑是将被乘数的一个乘法和一个乘法器的乘法乘以产生乘积。被乘数移位逻辑是移位被乘数的字。加法器将产品加到第一个运行总和以产生第二个运行总和。模数逻辑是有条件地添加一个单词的模数和第二个运行总和。模数移位逻辑是移动模数的单词。下一个处理元件包括用于乘法被乘数的移位的字和乘法器的下一位的逻辑。

3. 发明授权

US4312397A Process for forming shell molds 失效
标题翻译：成型模具的工艺
公开(公告)号：US4312397A
公开(公告)日：1982-01-26
申请号：US140296
申请日：1980-04-14
申请人： David L. Harris , Colin Taylor
发明人： David L. Harris , Colin Taylor
IPC分类号： B22C9/12 , B22C13/08
CPC分类号： B22C13/08 , B22C9/123
摘要： A pattern holder 12 and a sand tank 14 are rotatably mounted on a frame 16 so that the pattern holder can be inverted over and sealably mounted atop the sand tank. A vented pattern 26 is secured to the pattern holder and forms a first chamber between one side of the pattern and the interior of the pattern holder. A second chamber 90 is formed between the other side of the pattern and the interior of the sand tank when the pattern holder adjoins the sand tank. O-ring seals 32 and 80 isolate the chambers from the atmosphere so that a partial vacuum can be formed therein. A mixture 84 of sand and a gas-curable binder is provided in the sand tank so that the mixture will fall onto the pattern upon inverting the sand tank over the pattern holder. A flexible line 42 is provided for controllably introducing a gas catalyst into the chamber 38 in order to cure a portion of the sand-binder mixture to form a shell mold 94 of a predetermined thickness on a pattern face 36 of the pattern. Flexible lines 41 and 43 are provided for evacuating and purging the chamber 38 at different stages in the process.
摘要翻译：图案保持器12和砂槽14可旋转地安装在框架16上，使得图案保持器可以反转并密封地安装在砂箱顶部。通气图案26被固定到图案保持器，并且在图案的一侧和图案保持器的内部之间形成第一室。当图案保持器邻接砂箱时，第二室90形成在图案的另一侧和砂箱的内部之间。 O形圈密封件32和80将腔室与大气隔离，使得可以在其中形成部分真空。在沙箱中设置沙子和气体可固化粘合剂的混合物84，使得混合物在模型保持器上反转砂箱时落在图案上。提供柔性管线42用于将气体催化剂可控地引入室38中，以便固化一部分砂 - 粘合剂混合物，以在图案的图案面36上形成预定厚度的壳模94。柔性管线41和43被设置用于在该过程的不同阶段抽空和清洗腔室38。

4. 发明授权

US08335188B1 Method and system for handoffs between public and private wireless networks 有权
标题翻译：公共和私人无线网络之间切换的方法和系统
公开(公告)号：US08335188B1
公开(公告)日：2012-12-18
申请号：US12123010
申请日：2008-05-19
申请人： David L. Harris , Walter F. Rausch
发明人： David L. Harris , Walter F. Rausch
IPC分类号： H04W4/00
CPC分类号： H04W36/14 , H04W12/02 , H04W36/0061 , H04W48/08
摘要： A mobile station receives a neighbor list from a base station in an area of a public wireless network that borders a private wireless network. The neighbor list includes encrypted channel identifiers corresponding to private network channels transmitted by the private wireless network and unencrypted channel identifiers corresponding to public network channels transmitted by the public wireless network. If the mobile station does not subscribe to the private wireless network, the mobile station does not recognize the encrypted channel identifiers and simply ignores them. However, if the mobile station subscribes to the private wireless network, the mobile station decrypts the encrypted channel identifiers and determines whether it is able to initiate a handoff to any of the corresponding private network channels.
摘要翻译：移动台在与专用无线网络相邻的公共无线网络的区域中从基站接收邻居列表。邻居列表包括对应于由专用无线网络发送的专用网络信道的加密信道标识符和对应于由公共无线网络发送的公共网络信道的未加密信道标识符。如果移动台没有订阅专用无线网络，则移动台不识别加密的信道标识符，并且仅仅忽略它们。然而，如果移动台订阅专用无线网络，则移动台对加密的信道标识符进行解密，并且确定是否能够发起对任何相应专用网络信道的切换。

5. 发明申请

US20110096754A1 MULTI-FREQUENCY REAL-TIME DATA STREAM HANDOFF 有权
标题翻译：多频实时数据流处理
公开(公告)号：US20110096754A1
公开(公告)日：2011-04-28
申请号：US12606319
申请日：2009-10-27
申请人： David L. Harris , Walter F. Rausch
发明人： David L. Harris , Walter F. Rausch
IPC分类号： H04W36/30
CPC分类号： H04W36/02
摘要： A method of operating a communication system is disclosed. A time sensitive data stream is sent to a wireless device via a first wireless station. A handoff criteria is determined to have been satisfied. Based on the handoff criteria being satisfied, at least one control message is sent that instructs the wireless device to increase a buffer size associated with the time sensitive data stream.
摘要翻译：公开了一种操作通信系统的方法。时间敏感数据流经由第一无线站发送到无线设备。确定切换标准已被满足。基于满足切换标准，发送至少一个控制消息，其指示无线设备增加与时间敏感数据流相关联的缓冲器大小。

6. 发明授权

US06995039B2 Method and apparatus for electrostatically aligning integrated circuits 有权
标题翻译：集成电路静电对准的方法和装置
公开(公告)号：US06995039B2
公开(公告)日：2006-02-07
申请号：US10759923
申请日：2004-01-15
申请人： David L. Harris , Robert J. Drost , Ivan E. Sutherland
发明人： David L. Harris , Robert J. Drost , Ivan E. Sutherland
IPC分类号： H01L21/44
CPC分类号： H01L24/95 , H01L23/50 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2223/6622 , H01L2224/13012 , H01L2224/81121 , H01L2224/81801 , H01L2224/95145 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01039 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/0401
摘要： One embodiment of the present invention provides a system that uses electrostatic forces to align semiconductor chips relative to each other. The system operates by fabricating a first set of conductors on the top surface of a first chip and fabricating a corresponding second set of conductors on the top surface of a second chip. To align the chips, the system electrically charges the first set of conductors and the second set of conductors. The system also places the first chip face-to-face with the second chip, so that the first set of conductors is in close proximity to the second set of conductors. This allows electrostatic forces between the first set of conductors and the second set of conductors to bring the first chip into alignment with the second chip and to hold them in place.
摘要翻译：本发明的一个实施例提供一种使用静电力使半导体芯片相对于彼此对准的系统。该系统通过在第一芯片的顶表面上制造第一组导体并在第二芯片的顶表面上制造相应的第二组导体来操作。为了对准芯片，系统对第一组导体和第二组导体进行电荷充电。该系统还将第一芯片与第二芯片面对面地放置，使得第一组导体紧邻第二组导体。这允许第一组导体和第二组导体之间的静电力使第一芯片与第二芯片对准并将其保持就位。

7. 发明授权

US06580303B1 Datapath control circuit with adjustable delay elements 有权
标题翻译：数据路径控制电路具有可调延时元件
公开(公告)号：US06580303B1
公开(公告)日：2003-06-17
申请号：US09630443
申请日：2000-08-02
申请人： David L. Harris , Gregg Hoyer
发明人： David L. Harris , Gregg Hoyer
IPC分类号： H03H1126
CPC分类号： G06F9/3869
摘要： A control circuit for a FIFO datapath is described. The control circuit consists of a chain of Muller C-elements with adjustable delay elements placed between the output of each Muller C-element and one of the inputs of the preceding and successive Muller C-elements. The adjustable delay elements allow the control circuit to match the delays of processing elements in the datapath, thereby creating overall faster operation.
摘要翻译：描述了用于FIFO数据通路的控制电路。控制电路由一串Muller C元件组成，其中可调节的延迟元件放置在每个Muller C元件的输出和前一个和连续Muller C元件的输入之一之间。可调延迟元件允许控制电路匹配数据路径中的处理元件的延迟，从而创建总体更快的操作。

8. 发明授权

US07615900B1 Power generator for electronic devices 失效
标题翻译：电子设备发电机
公开(公告)号：US07615900B1
公开(公告)日：2009-11-10
申请号：US11689949
申请日：2007-03-22
申请人： David L. Harris
发明人： David L. Harris
IPC分类号： H02K7/10
CPC分类号： H02K35/02
摘要： A power generator comprises a coil with having ends connected to electrical contacts, a magnet mounted on a slide rod placed surrounded by the coil and having a positive pole and a negative pole and configured to slide between the two ends of said rod to generate an electrical power in the coil by electromagnetic induction on movement of the magnet inside the coil, a first magnetic bumper located at a first end of the two ends of the slide rod and having a positive pole facing the positive pole of the magnet, a second magnetic bumper located at a second end of the two ends of the slide rod and having a negative pole facing the negative pole of the magnet, and an electronic interface circuit for converting an output power of said electrical contacts of the coil to a power input of an electronic device.
摘要翻译：发电机包括具有端部连接到电触头的线圈，安装在滑动杆上的磁体，该滑动杆由线圈包围并具有正极和负极并构造成在所述杆的两端之间滑动以产生电通过电磁感应在线圈内的磁体的运动中的线圈中的动力，位于滑动杆的两端的第一端并且具有面向磁体的正极的正极的第一磁性缓冲器，第二磁性保险杠位于所述滑动杆的两端的第二端并且具有面对所述磁体的负极的负极，以及电子接口电路，用于将所述线圈的所述电触点的输出功率转换为电子的电力输入设备。

9. 发明授权

US07152089B2 Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks 有权
标题翻译：并行前缀网络在逻辑电平，扇出和接线架之间进行权衡
公开(公告)号：US07152089B2
公开(公告)日：2006-12-19
申请号：US10431036
申请日：2003-05-05
申请人： David L. Harris
发明人： David L. Harris
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F7/74 , G06F2207/5063
摘要： A circuit that performs a prefix computation. This circuit includes an N-bit prefix network of prefix cells arranged into L+l logic levels, wherein the prefix network computes N outputs {YN, . . . , Y1} from N inputs {XN, . . . , X1} using an associative two-input operator ∘, such that, Y1=X1, Y2=X2∘X1, Y3=X3∘X2∘X1, . . . , and YN=XN∘XN−1∘ . . . ∘X2∘X1. Within this prefix network, each prefix cell has a fanout of at most 2f+1, and there are at most 2t horizontal wiring tracks between each logic level. Additionally, l+f+t=L−1, and unlike existing prefix circuits, 1>0,f>0, and t>0.
摘要翻译：执行前缀计算的电路。该电路包括布置成L + 1逻辑电平的前缀单元的N位前缀网络，其中前缀网络计算N个输出{Y N N N，。。，Y N 1，N N，N 2，...，N N，。。使用关联的双输入算子○，使得Y 1→X 1，Y 2，...，X 2， SUB> = X 2 2 X 1，Y 3，X 3，X 3，X 2， SUB>ΟX1 ，。。。，并且Y N N = X N N N N-1。。。 ΟX2 1 。在该前缀网络内，每个前缀单元具有至多2×F + 1的扇出，并且在每个逻辑电平之间存在至多2个水平布线轨道。另外，l + f + t = L-1，与现有的前缀电路不同，1> 0，f> 0和t> 0。

10. 发明授权

US06970034B1 Method and apparatus for reducing power consumption due to gate leakage during sleep mode 有权
标题翻译：用于在睡眠模式期间减少由于门泄漏引起的功耗的方法和装置
公开(公告)号：US06970034B1
公开(公告)日：2005-11-29
申请号：US10616048
申请日：2003-07-07
申请人： David L. Harris
发明人： David L. Harris
IPC分类号： H03K19/00 , G05F1/10
CPC分类号： H03K19/0016
摘要： One embodiment of the present invention provides a system that achieves low gate leakage current in an integrated circuit during sleep mode. Upon entering sleep mode, the system reduces the power supply voltage applied to the integrated circuit to a low voltage level, wherein the low voltage level is low enough to provide a low gate leakage current, but is high enough to maintain state in the integrated circuit.
摘要翻译：本发明的一个实施例提供了一种在睡眠模式期间在集成电路中实现低栅极泄漏电流的系统。在进入睡眠模式时，系统将施加到集成电路的电源电压降低到低电压电平，其中低电压电平足够低以提供低栅极泄漏电流，但是足够高以维持集成电路中的状态。

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