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1. 发明申请

US20090315839A1 PHYSICS SIMULATION-BASED INTERACTION FOR SURFACE COMPUTING 有权
标题翻译：基于物理模拟的表面计算相互作用
公开(公告)号：US20090315839A1
公开(公告)日：2009-12-24
申请号：US12203350
申请日：2008-09-03
申请人： Andrew David Wilson , Shahram Izadi , Armando Garcia-Mendoza , David Kirk , Otmar Hilliges
发明人： Andrew David Wilson , Shahram Izadi , Armando Garcia-Mendoza , David Kirk , Otmar Hilliges
IPC分类号： G06F3/041
CPC分类号： G06F17/5009 , A63F13/214 , A63F13/57 , G06F3/0425 , G06F3/0488 , G06F2203/04104 , G06F2217/16 , G06T7/20 , G06T2207/30196
摘要： The claimed subject matter provides a system and/or a method that facilitates enhancing interactive surface technologies for data manipulation. A surface detection component can employ a multiple contact surfacing technology to detect a surface input, wherein the detected surface input enables a physical interaction with a portion of displayed data that represents a corporeal object. A physics engine can integrate a portion of Newtonian physics into the interaction with the portion of displayed data in order to model at least one quantity related associated with the corporeal object, the quantity is at least one of a force, a mass, a velocity, or a friction.
摘要翻译：所要求保护的主题提供了有助于增强用于数据操纵的交互式表面技术的系统和/或方法。表面检测部件可以采用多接触表面技术来检测表面输入，其中检测到的表面输入使得能够与表示物体对象的显示数据的一部分进行物理交互。物理引擎可将牛顿物理学的一部分整合到与所显示的数据的部分的相互作用中，以便对与物体对象相关联的至少一个数量进行建模，该量是力，质量，速度，或摩擦。

2. 发明授权

US07620030B1 Method and apparatus for terminating/generating physically and virtually concatenated signals 有权
标题翻译：用于终止/产生物理和虚拟级联信号的方法和装置
公开(公告)号：US07620030B1
公开(公告)日：2009-11-17
申请号：US10993138
申请日：2004-11-19
申请人： David Kirk
发明人： David Kirk
IPC分类号： H04L12/28
CPC分类号： H04J3/1611 , H04J2203/0094 , H04J2203/0096
摘要： A SONET signal is terminated by pointer processing a physically concatenated SONET signal to output a pointer processed physically concatenated SONET signal. Virtual concatenation-related byte markers (for example, H4 and J1) are then inserted into the pointer processed physically concatenated SONET signal. Virtual concatenation overhead data (for example, MFI and SEQ#) is then inserted into the pointer processed physically concatenated SONET signal so as to produce a converted virtually concatenated SONET signal. Virtual concatenation logic processing is then performed on the converted virtually concatenated signal. In this way, a physically concatenated SONET signal can be received and processed on a single integrated circuit with a virtual concatenation logic processor receiver this obviating the need for including a separate physically concatenated logic processing receiver or multiple integrated circuit chips.
摘要翻译：通过指针处理物理连接的SONET信号来终止SONET信号，以输出物理连接的SONET信号的指针。然后将虚拟级联相关的字节标记（例如，H4和J1）插入指针处理的物理连接的SONET信号中。然后将虚拟级联开销数据（例如，MFI和SEQ＃）插入经处理的物理连接的SONET信号中，以产生转换的虚拟级联SONET信号。然后对转换的虚拟级联信号执行虚拟级联逻辑处理。以这种方式，物理级联的SONET信号可以在具有虚拟级联逻辑处理器接收器的单个集成电路上被接收和处理，从而避免了包括单独的物理级联逻辑处理接收器或多个集成电路芯片的需要。

3. 发明申请

US20080143730A1 HIERARCHICAL PROCESSOR ARRAY 有权
标题翻译：分层处理器阵列
公开(公告)号：US20080143730A1
公开(公告)日：2008-06-19
申请号：US11933993
申请日：2007-11-01
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06F15/00
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

4. 发明授权

US07136068B1 Texture cache for a computer graphics accelerator 失效
标题翻译：纹理缓存为计算机图形加速器
公开(公告)号：US07136068B1
公开(公告)日：2006-11-14
申请号：US09056656
申请日：1998-04-07
申请人： Curtis Priem , Gopal Solanki , David Kirk
发明人： Curtis Priem , Gopal Solanki , David Kirk
IPC分类号： G06F15/16
CPC分类号： G06T1/60
摘要： A method and apparatus which includes a graphics accelerator, circuitry responsive to pixel texture coordinates to select texels and generate therefrom a texture value for any pixel the color of which is to be modified by a texture, and a cache for texels for use by the circuitry to generate texture value for any pixel.
摘要翻译：一种包括图形加速器的方法和装置，响应于像素纹理坐标来选择纹理并从其生成用于由颜色修饰其颜色的任何像素的纹理值的电路，以及由电路使用的纹素的高速缓存以生成任何像素的纹理值。

5. 发明授权

US06920604B2 Systems and methods for high speed serial encoding and decoding for data and control interfaces 有权
标题翻译：用于数据和控制接口的高速串行编码和解码的系统和方法
公开(公告)号：US06920604B2
公开(公告)日：2005-07-19
申请号：US10117208
申请日：2002-04-08
申请人： Matthew Coakeley , Erik Trounce , David Kirk , Michael Vandegriend , Richard DeBoer , Nizar Rida
发明人： Matthew Coakeley , Erik Trounce , David Kirk , Michael Vandegriend , Richard DeBoer , Nizar Rida
IPC分类号： H03M13/09 , H03M13/11 , G06F11/10 , H03M13/03
CPC分类号： H03M13/098
摘要： Systems and methods for encoding and decoding serial bit streams are provided. A parity bit is computed for each nibble, with the parity alternating between odd and even in a regular manner for normal data, and with parity having predetermined different patterns to indicate the start of a packet or the end of a packet. Special code words indicate the idle state and an error state. In some systems an extra vertical parity channel is provided in association with a group of data channels, the vertical parity channel effectively providing a protection channel.
摘要翻译：提供了用于编码和解码串行比特流的系统和方法。为每个半字节计算奇偶校验位，奇偶校验在正常数据之间以正常方式交替奇偶校验位，并且奇偶校验具有预定的不同模式以指示分组的开始或分组的结束。特殊代码字表示空闲状态和错误状态。在一些系统中，与一组数据信道相关联地提供了额外的垂直奇偶校验信道，垂直奇偶校验信道有效地提供保护信道。

6. 发明申请

US20120026175A1 HIERARCHICAL PROCESSOR ARRAY 有权
标题翻译：分层处理器阵列
公开(公告)号：US20120026175A1
公开(公告)日：2012-02-02
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件多种图形操作与不同阶段的图形处理相关联。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

7. 发明授权

US08077174B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08077174B2
公开(公告)日：2011-12-13
申请号：US11933993
申请日：2007-11-01
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

8. 发明申请

US20070141201A1 Method of preventing discoloration of dough, dough compositions, and dough products 审中-公开
标题翻译：防止面团，面团组合物和面团产品变色的方法
公开(公告)号：US20070141201A1
公开(公告)日：2007-06-21
申请号：US11653666
申请日：2007-01-16
申请人： David Domingues , David Kirk
发明人： David Domingues , David Kirk
IPC分类号： A21D2/00
CPC分类号： A21D10/025 , A21D2/181 , A21D4/00 , A21D6/001 , A21D8/042 , B65D81/20
摘要： Described are dough compositions, dough products, and related methods for preventing discoloration of dough compositions, including particular embodiments involving a packaged dough product suitable for storage under low pressure conditions, and embodiments wherein the dough comprises an oxidoreductase enzyme such as glucose oxidase, and optionally catalase.
摘要翻译：描述了面团组合物，面团产品和用于防止面团组合物变色的相关方法，包括适用于在低压条件下储存的包装面团产品的具体实施方案，以及其中面团包含氧化还原酶如葡萄糖氧化酶和任选地过氧化氢酶。

9. 发明授权

US07038692B1 Method and apparatus for providing a vertex cache 有权
标题翻译：提供顶点缓存的方法和装置
公开(公告)号：US07038692B1
公开(公告)日：2006-05-02
申请号：US10042733
申请日：2000-10-25
申请人： Curtis Priem , David Kirk
发明人： Curtis Priem , David Kirk
IPC分类号： G09G5/36 , G09G5/39
CPC分类号： G06T15/005 , G06T1/60
摘要： A method for caching data defining vertices of a polygon to be displayed by an input/output display device including the steps of providing an index by a vertex for which data is to be cached, storing data defining attributes of a polygon at a vertex in a cache under the index provided, issuing a command signifying a polygon to be manipulated by indicating indices of the vertices of the polygon for which data is cached.
摘要翻译：一种用于缓存要由输入/输出显示设备显示的多边形的顶点的数据的缓存数据的方法，包括以下步骤：由数据要被缓存的顶点提供索引，存储定义多边形的属性的数据缓存在所提供的索引下，通过指示数据被高速缓存的多边形的顶点的索引来发出表示要被操纵的多边形的命令。

10. 发明授权

US06075544A Method and apparatus for accelerating rendering by coalescing data accesses 失效
标题翻译：通过合并数据访问来加速渲染的方法和装置
公开(公告)号：US06075544A
公开(公告)日：2000-06-13
申请号：US55564
申请日：1998-04-06
申请人： Chris Malachowsky , Curtis Priem , David Kirk
发明人： Chris Malachowsky , Curtis Priem , David Kirk
IPC分类号： G09G5/39 , G09G5/393 , G09G5/36
CPC分类号： G09G5/393 , G09G5/39
摘要： A circuit for accelerating processing of pixel data being provided to a frame buffer comprising circuitry for determining that pixel values vary linearly over a scan line of a polygon to be rendered, linear interpolation circuitry for providing pixel values using a process of linear interpolation between accurately determined pixel values, and a circuit for collecting pixel values to be written to a frame buffer until a significant number of pixel values may be written together.
摘要翻译：一种用于加速处理像素数据的电路，其被提供给一个帧缓冲器，该帧缓冲器包括用于确定像素值在要渲染的多边形的扫描线上线性变化的电路;线性内插电路，用于使用精确确定的线性内插过程来提供像素值像素值，以及用于收集要写入帧缓冲器的像素值直到可以将大量像素值一起写入的电路。

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