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1. 发明申请

US20100138640A1 Reset synchronisation 有权
标题翻译：重置同步
公开(公告)号：US20100138640A1
公开(公告)日：2010-06-03
申请号：US12314020
申请日：2008-12-02
申请人： David Michael Gilday , Peter Logan Harrod
发明人： David Michael Gilday , Peter Logan Harrod
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.
摘要翻译：公开了复位控制电路，用于控制用于复位电路的至少第一部分的第一复位信号和用于复位所述电路的至少第二部分的另外的复位信号，所述复位控制电路包括：用于接收输入第一复位信号; 用于接收输入进一步复位信号的输入; 用于输出输出第一复位信号的输出; 以及用于输出输出进一步复位信号的输出; 所述复位控制电路响应于当所述输入进一步复位信号被确定以延迟所述输出第一复位信号的失效时检测到所述输入第一复位信号的失效，以使所述输出第一复位信号在所述输入的同时或晚于所述输入进一步复位信号。

2. 发明授权

US08250351B2 Synchronization of two independent reset signals 有权
标题翻译：两个独立复位信号的同步
公开(公告)号：US08250351B2
公开(公告)日：2012-08-21
申请号：US12314020
申请日：2008-12-02
申请人： David Michael Gilday , Peter Logan Harrod
发明人： David Michael Gilday , Peter Logan Harrod
IPC分类号： G06F15/177
CPC分类号： G06F1/24
摘要： Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.
摘要翻译：公开了复位控制电路，用于控制用于复位电路的至少第一部分的第一复位信号和用于复位所述电路的至少第二部分的另外的复位信号，所述复位控制电路包括：用于接收输入第一复位信号; 用于接收输入进一步复位信号的输入; 用于输出输出第一复位信号的输出; 以及用于输出输出进一步复位信号的输出; 所述复位控制电路响应于当所述输入进一步复位信号被断言以延迟所述输出第一复位信号的失效时检测到所述输入第一复位信号的失效，使得所述输出第一复位信号在所述输入的同时或晚于所述输入进一步复位信号。

3. 发明授权

US07949914B2 Diagnostic mode switching 有权
标题翻译：诊断模式切换
公开(公告)号：US07949914B2
公开(公告)日：2011-05-24
申请号：US12656434
申请日：2010-01-29
申请人： Peter Logan Harrod , Edmond John Simon Ashfield , Thomas Sean Houlihane , Paul Kimelman , Simon John Craske , Michael John Williams
发明人： Peter Logan Harrod , Edmond John Simon Ashfield , Thomas Sean Houlihane , Paul Kimelman , Simon John Craske , Michael John Williams
IPC分类号： G01R31/28
CPC分类号： G01R31/318572
摘要： A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.
摘要翻译：描述了具有JTAG诊断单元和串联线诊断单元的系统。监视器单元连接到诊断单元之间共享的数据连接。在共享数据连接上检测到的特殊模式用于在诊断单元变为活动的诊断模式之间切换。

4. 发明授权

US07743294B2 Diagnostic mode switching 有权
公开(公告)号：US07743294B2
公开(公告)日：2010-06-22
申请号：US11601849
申请日：2006-11-20
申请人： Peter Logan Harrod , Edmond John Simon Ashfield , Thomas Sean Houlihane , Paul Kimelman , Simon John Craske , Michael John Williams
发明人： Peter Logan Harrod , Edmond John Simon Ashfield , Thomas Sean Houlihane , Paul Kimelman , Simon John Craske , Michael John Williams
IPC分类号： G01R31/28
CPC分类号： G01R31/318572
摘要： A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

5. 发明申请

US20070167785A1 Diagnostic mode switching 有权
标题翻译：诊断模式切换
公开(公告)号：US20070167785A1
公开(公告)日：2007-07-19
申请号：US11601849
申请日：2006-11-20
申请人： Peter Logan Harrod , Edmond John Simon Ashfield , Thomas Sean Houlihane , Paul Kimelman , Simon John Craske , Michael John Williams
发明人： Peter Logan Harrod , Edmond John Simon Ashfield , Thomas Sean Houlihane , Paul Kimelman , Simon John Craske , Michael John Williams
IPC分类号： A61B8/00
CPC分类号： G01R31/318572
摘要： A system is described having a JTAG diagnostic unit 2 and a serial wire diagnostic unit 4. A watcher unit 6 is connected to a data connection 14 shared between the diagnostic units 2, 4. Special patterns detected upon the shared data connection 14 serve to switch between diagnostic modes with respective ones of the diagnostic units 2, 4 becoming active.
摘要翻译：描述了具有JTAG诊断单元2和串联线诊断单元4的系统。观察者单元6连接到在诊断单元2,4之间共享的数据连接14.在共享数据连接14上检测到的特殊模式用于在诊断单元2,4中的相应诊断单元2,4变为活动的诊断模式之间切换。

6. 发明授权

US07085978B2 Validating test signal connections within an integrated circuit 有权
标题翻译：验证集成电路内的测试信号连接
公开(公告)号：US07085978B2
公开(公告)日：2006-08-01
申请号：US10244561
申请日：2002-09-17
申请人： Teresa Louise McLaurin , Peter Logan Harrod , Raul Armando Garibay
发明人： Teresa Louise McLaurin , Peter Logan Harrod , Raul Armando Garibay
IPC分类号： G01R31/28
CPC分类号： G01R31/04
摘要： Testing of the test signal connections to a functional block of circuitry within an integrated circuit is made using wrapper serial scan chain cells of a wrapper serial scan chain. These wrapper cells can then be used to validate that the correct signals are reaching test signal inputs and the correct signals are reaching their destination from test signal outputs when that functional block of circuitry is incorporated within a larger design, e.g., a system-on-chip design.
摘要翻译：测试信号与集成电路中的电路功能块的连接是使用包装器串行扫描链的封装序列扫描链单元进行的。然后可以使用这些封装单元来验证正确的信号正在达到测试信号输入，并且当电路的功能块被并入更大的设计中时，正确的信号从测试信号输出到达它们的目的地，芯片设计。

7. 发明申请

US20100223518A1 Diagnostic mode switching 有权
标题翻译：诊断模式切换
公开(公告)号：US20100223518A1
公开(公告)日：2010-09-02
申请号：US12656434
申请日：2010-01-29
申请人： Peter Logan Harrod , Edmond John Simon Ashfield , Thomas Sean Houlihane , Paul Kimelman , Simon John Craske , Michael John Williams
发明人： Peter Logan Harrod , Edmond John Simon Ashfield , Thomas Sean Houlihane , Paul Kimelman , Simon John Craske , Michael John Williams
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318572
摘要： A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.
摘要翻译：描述了具有JTAG诊断单元和串联线诊断单元的系统。监视器单元连接到诊断单元之间共享的数据连接。在共享数据连接上检测到的特殊模式用于在诊断单元变为活动的诊断模式之间切换。

8. 发明授权

US07373550B2 Generation of a computer program to test for correct operation of a data processing apparatus 有权
标题翻译：生成用于测试数据处理装置的正确操作的计算机程序
公开(公告)号：US07373550B2
公开(公告)日：2008-05-13
申请号：US11049296
申请日：2005-02-03
申请人： Jonathan William Brawn , Simon John Craske , Peter Logan Harrod , Eric Jason Furbish
发明人： Jonathan William Brawn , Simon John Craske , Peter Logan Harrod , Eric Jason Furbish
IPC分类号： G06F11/00
CPC分类号： G06F11/3688
摘要： Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate software built in self test computer programs and compare the simulated execution, such to deliberately introduced test faults, with expected execution outcomes previously derived for that candidate program to determine the sensitivity of that candidate program to the faults which are introduced. This score can be fed back into the genetic algorithm mutation to converge the mutation process upon appropriately fault sensitive software built in self test program code.
摘要翻译：使用遗传算法14技术生成内置于自检计算机程序12中的软件。故障模拟器20用于模拟内置在自检计算机程序中的候选软件，并将模拟执行（例如故意引入的测试故障）与先前为该候选程序导出的预期执行结果进行比较，以确定该候选程序对故障的灵敏度介绍。该分数可以反馈到遗传算法突变中，以将变异过程收敛于内置于自检程序代码中的适当的故障敏感软件。

9. 发明授权

US6052774A Apparatus and method for identifying exception routines indicated by instruction address issued with an instruction fetch command 失效
标题翻译：用于识别由指令获取命令发出的指令地址指示的异常例程的装置和方法
公开(公告)号：US6052774A
公开(公告)日：2000-04-18
申请号：US035838
申请日：1998-03-06
申请人： Simon Anthony Segars , Peter Logan Harrod , Andrew John Merritt
发明人： Simon Anthony Segars , Peter Logan Harrod , Andrew John Merritt
IPC分类号： G06F11/28 , G06F11/36 , G06F11/00
CPC分类号： G06F11/3656
摘要： The present invention provides a debugger interface unit for a data processing apparatus, comprising a control register having a number of fields, each field corresponding to a particular exception routine, and each field being settable to indicate that the debugger wishes to identify an access to the corresponding exception routine. Further, an exception routine catch logic is provided to receive a first signal when a processor core within the data processing apparatus issues an instruction fetch command for an exception routine, and to determine from an instruction address issued with the instruction fetch command which exception routine is being fetched. In addition, the catch logic is arranged to reference the field of the control register corresponding to the determined exception routine to determine if that field has been set, and if the field has been set, to output a breakpoint signal to the processor core.The above approach provides a particularly efficient technique for identifying accesses to exception routines when debugging software, such identification being independent of the base address of the exception routines.
摘要翻译：本发明提供了一种用于数据处理设备的调试器接口单元，包括具有多个字段的控制寄存器，每个字段对应于特定异常例程，并且每个字段都可设置为指示调试器希望识别对相应的例外程序。此外，当数据处理设备内的处理器核心发出用于异常例程的指令获取命令时，提供异常例程捕捉逻辑以接收第一信号，并且从从指令获取命令发出的指令地址确定该异常例程是被抓取此外，捕获逻辑被布置为引用与所确定的异常例程相对应的控制寄存器的字段，以确定该字段是否已被设置，并且如果该字段已被设置，则将断点信号输出到处理器核。上述方法提供了一种特别有效的技术，用于在调试软件时识别对异常例程的访问，这种标识独立于异常例程的基址。

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