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1. 发明授权

US07518248B2 Inductive filters and methods of fabrication therefor 有权
标题翻译：电感式滤波器及其制造方法
公开(公告)号：US07518248B2
公开(公告)日：2009-04-14
申请号：US11462611
申请日：2006-08-04
申请人： Yuan-Liang Li , David G. Figueroa
发明人： Yuan-Liang Li , David G. Figueroa
IPC分类号： H01L23/52
CPC分类号： H01F17/0033 , H01F41/041 , H01L23/49822 , H01L23/49838 , H01L2224/16 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15312 , H05K1/115 , H05K1/165 , H05K3/06 , H05K3/42 , H05K2201/086 , H05K2201/097 , H05K2201/1006 , H05K2203/0723 , H01L2224/0401
摘要： A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure. A method of producing an interconnected series of PTH vias includes providing a dielectric board having a series of holes. In some embodiments, the board includes an embedded ferromagnetic material pattern. The holes and the top and bottom surface of the dielectric board have a conductive material thereupon. Portions of the conductive material are selectively removed, resulting in the embedded inductive filter and/or transformer structure.
摘要翻译：一系列电镀通孔（PTH）通孔在电介质板的顶表面和底表面之间交替的迹线互连。该系列中的PTH通孔可以定位成产生共线感应滤波器，线圈型感应滤波器或变压器。在一个实施例中，多个电隔离的互连PTH通孔系列可用作多相感应滤波器。在另一个实施例中，多个互连的PTH通孔系列通过导电材料的连接部分电连接，导致低电阻感应滤波器。铁磁材料图案可以嵌入电介质板中以增强互连通孔结构的感应特性。在一个实施例中，闭合端图案具有围绕图案卷绕的两系列互连的通孔，从而形成嵌入式变压器结构。制造互连的PTH通孔系列的方法包括提供具有一系列孔的电介质板。在一些实施例中，板包括嵌入的铁磁材料图案。电介质板的孔和顶表面和底表面之间具有导电材料。选择性地去除导电材料的部分，从而产生嵌入的感应滤波器和/或变压器结构。

2. 发明授权

US07492605B2 Power plane to reduce voltage difference between connector power pins 失效
标题翻译：电源平面，以减少连接器电源引脚之间的电压差
公开(公告)号：US07492605B2
公开(公告)日：2009-02-17
申请号：US11473359
申请日：2006-06-22
申请人： Yuan-Liang Li , Jayashree Kar , David G. Figueroa , Dong Zhong
发明人： Yuan-Liang Li , Jayashree Kar , David G. Figueroa , Dong Zhong
IPC分类号： H05K1/11 , H05K1/00
CPC分类号： H05K1/0265 , H05K1/0254 , H05K2201/044 , H05K2201/0784 , H05K2201/093 , H05K2201/0969
摘要： A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.
摘要翻译：包括供电电源插座，第一连接器电源插座和第二电源插座的电力平面，其中电源电极插座和第一连接器电源插座之间的第一电阻基本上等于第二电阻在电源插座和第二连接器电源插座之间。

3. 发明授权

US07176565B2 Capacitors having separate terminals on three or more sides 失效
标题翻译：电容器在三面或三面以上具有独立的端子
公开(公告)号：US07176565B2
公开(公告)日：2007-02-13
申请号：US10006188
申请日：2001-12-03
申请人： Yuan-Liang Li , David G. Figueroa , Chee-Yee Chung
发明人： Yuan-Liang Li , David G. Figueroa , Chee-Yee Chung
IPC分类号： H01L23/34
CPC分类号： H01G4/232
摘要： A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.
摘要翻译：多层电容器包括在至少三个侧面上以及多达六个侧面的分开的端子。根据目标应用，电容器可以以大量不同的配置，类型和尺寸制造。设置在电容器的不同侧上的单独的端子可以容易地耦合到各种不同的相邻导体，例如模具端子（包括无扰动端子或条），IC封装端子（包括焊盘或条），以及端子相邻的分立元件。还描述了制造方法以及将电容器应用于电子组件。

4. 发明授权

US06992387B2 Capacitor-related systems for addressing package/motherboard resonance 有权
标题翻译：用于寻址封装/主板谐振的电容器相关系统
公开(公告)号：US06992387B2
公开(公告)日：2006-01-31
申请号：US10602096
申请日：2003-06-23
申请人： Jennifer A. Hester , Yuan-Liang Li , Michael M. Desmith , David G. Figueroa , Dong Zhong
发明人： Jennifer A. Hester , Yuan-Liang Li , Michael M. Desmith , David G. Figueroa , Dong Zhong
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H05K1/114 , H01G4/385 , H01L23/49838 , H01L23/642 , H01L2224/16 , H01L2224/16227 , H01L2924/00014 , H01L2924/01021 , H01L2924/01057 , H01L2924/15312 , H01L2924/19106 , H01L2924/3011 , H05K1/0231 , H05K2201/09263 , H05K2201/09345 , H05K2201/0979 , H05K2201/10636 , Y02P70/611 , H01L2224/0401
摘要： According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.
摘要翻译：根据一些实施例，器件包括电耦合到与第一极性相关联的第一端子的第一导电平面和与第一极性相关联的第二端子，电耦合到与第二极性相关联的第三端子的第二导电平面，以及设置在所述第一导电平面和所述第二导电平面之间的电介质。在第一端子和第三端子之间存在第一电容，在第二端子和第三端子之间存在第二电容，并且第一电容和第二电容可以是基本不相似的。

5. 发明授权

US06914334B2 Circuit board with trace configuration for high-speed digital differential signaling 失效
标题翻译：具有高速数字差分信号跟踪配置的电路板
公开(公告)号：US06914334B2
公开(公告)日：2005-07-05
申请号：US10167904
申请日：2002-06-12
申请人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David G. Figueroa
发明人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David G. Figueroa
IPC分类号： H01L23/498 , H01L23/66 , H01P3/08 , H05K1/02 , H01L23/48
CPC分类号： H01P3/081 , H01L23/49822 , H01L23/49838 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H05K1/0242 , H05K1/0245 , H05K1/0265 , H05K3/4644 , H05K2201/0715 , H05K2201/09236 , H05K2201/09672 , H05K2201/0979 , H05K2201/098 , H05K2203/0733 , H01L2924/00
摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.
摘要翻译：用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。在一个实施例中，电路板具有设置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。第二组与非导电材料与第一组分离。第一组和第二组的相应迹线可以是堆叠配置。在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。在其它实施例中，迹线构造具有“T形”和“L形”横截面。

6. 发明授权

US06811410B2 Integrated circuit socket with capacitors and shunts 失效
标题翻译：集成电路插座，带电容器和分流器
公开(公告)号：US06811410B2
公开(公告)日：2004-11-02
申请号：US10156909
申请日：2002-05-28
申请人： David G. Figueroa , Yuan-Liang Li
发明人： David G. Figueroa , Yuan-Liang Li
IPC分类号： H01R1200
CPC分类号： H05K1/0231 , H01R12/7088 , H01R13/6625 , H01R31/08 , H01R33/765 , H05K2201/10325 , H05K2201/10689
摘要： An integrated circuit socket with capacitors and shunts is disclosed. According to one embodiment of the invention, a socket is divided into a shunt area, a socket pin area, and a land side capacitor area. The shunt area may contain a variable number of power shunts, ground shunts, and capacitors. The capacitors are connected across, and serve to decouple, power shunts and ground shunts. The shunts are to supply an electrical current from the capacitors to an integrated circuit device. The socket pin area may be surrounded by a metal fence serving as to lessen electromagnetic interference and as a ground and/or signal reference. The fence may be divided into sub-areas each comprising a coaxial differential signal pin opening pair. In alternate designs, an elongated power bar may serve as a power or ground shunt and may be used with several capacitors.
摘要翻译：公开了一种具有电容器和分流器的集成电路插座。根据本发明的一个实施例，插座被分成分流区域，插座引脚区域和陆侧电容器区域。分流区域可能包含可变数量的功率分流器，接地分流器和电容器。电容器连接在一起，并用于去耦电源分流器和接地分流器。分流器将从电容器向集成电路器件提供电流。插座针脚区域可以被金属围栏包围，以减少电磁干扰，并且作为接地和/或信号参考。栅栏可以被划分成各自包括同轴差分信号针开口对的子区域。在替代设计中，细长的电源杆可以用作电源或接地分流器，并且可以与多个电容器一起使用。

7. 发明授权

US06559484B1 Embedded enclosure for effective electromagnetic radiation reduction 有权
标题翻译：嵌入式外壳，有效减少电磁辐射
公开(公告)号：US06559484B1
公开(公告)日：2003-05-06
申请号：US09672619
申请日：2000-09-29
申请人： Yuan-Liang Li , Chee-Yee Chung , David G. Figueroa
发明人： Yuan-Liang Li , Chee-Yee Chung , David G. Figueroa
IPC分类号： H01L2710
CPC分类号： H01L23/49822 , H01L23/49838 , H01L23/50 , H01L2224/16 , H01L2224/16227 , H01L2224/16265 , H01L2224/17181 , H01L2924/01019 , H01L2924/01087 , H01L2924/15311 , H01L2924/15312 , H01L2924/19104 , H01L2924/19106 , H01L2924/3025
摘要： In one embodiment of the invention, an embedded enclosure includes a power plane and first and second ground planes. The power plane has a power surface and a power periphery, and couples power to signals of an integrated circuit operating at a fundamental frequency. The first and second ground planes have first and second ground surfaces and first and second ground peripheries, respectively. The first and second ground planes couple ground to the signals. The first and second ground planes are separated from the power plane by first and second distances, respectively. The first and second ground surfaces are larger than the power surface. The first and second ground peripheries extend at least third and fourth distances from the power periphery, respectively. The third and fourth distances are N and M times larger than the first and second distances, respectively.
摘要翻译：在本发明的一个实施例中，嵌入式外壳包括电源平面以及第一和第二接地平面。电力平面具有功率表面和功率外围，并且将功率耦合到以基频工作的集成电路的信号。第一和第二接地平面分别具有第一和第二接地表面以及第一和第二接地外围。第一和第二接地平面将信号耦合到地面。第一和第二接地平面分别与动力平面分开第一和第二距离。第一和第二接地表面大于功率表面。第一和第二接地周边分别从功率周边延伸至少第三和第四距离。第三和第四距离分别比第一和第二距离大N和M倍。

8. 发明授权

US06388207B1 Electronic assembly with trench structures and methods of manufacture 有权
标题翻译：具有沟槽结构的电子组装和制造方法
公开(公告)号：US06388207B1
公开(公告)日：2002-05-14
申请号：US09751356
申请日：2000-12-29
申请人： David G. Figueroa , Michael Walk , Yuan-Liang Li , Robert L. Sankman
发明人： David G. Figueroa , Michael Walk , Yuan-Liang Li , Robert L. Sankman
IPC分类号： H01R2368
CPC分类号： H05K1/115 , H01L23/49805 , H01L23/50 , H01L23/5383 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01078 , H01L2924/01087 , H01L2924/09701 , H01L2924/15311 , H05K1/0263 , H05K1/162 , H05K3/4602 , H05K2201/09854 , H01L2224/05599
摘要： To accommodate the operational and structural requirements of high performance integrated circuits, an integrated circuit package includes conductive trenches that are formed within a substrate. The trenches provide increased current carrying capacity, lower inductance, higher capacitance, and single and/or dual reference planes for signal conductors. Trench structures can be provided at various locations within the substrate, such as adjacent to signal conductors and embedded capacitors, as well as on the substrate periphery to couple the package to a socket. Trenches can be formed by routing, drilling, imprinting, and/or microperforation. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
摘要翻译：为了适应高性能集成电路的操作和结构要求，集成电路封装包括形成在衬底内的导电沟槽。沟槽提供增加的载流能力，较低的电感，更高的电容，以及用于信号导体的单和/或双参考平面。沟槽结构可以设置在衬底内的各个位置，例如与信号导体和嵌入式电容器相邻，以及在衬底周边上以将封装耦合到插座。可以通过布线，钻孔，压印和/或微穿孔形成沟槽。还描述了制造方法以及将包装应用于电子组件和电子系统。

9. 发明授权

US07417872B2 Circuit board with trace configuration for high-speed digital differential signaling 失效
标题翻译：具有高速数字差分信号跟踪配置的电路板
公开(公告)号：US07417872B2
公开(公告)日：2008-08-26
申请号：US11459951
申请日：2006-07-26
申请人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David G. Figueroa
发明人： Yuan-Liang Li , Jiangqi He , Dong Zhong , David G. Figueroa
IPC分类号： H05H1/11
CPC分类号： H01P3/081 , H01L23/49822 , H01L23/49838 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H05K1/0242 , H05K1/0245 , H05K1/0265 , H05K3/4644 , H05K2201/0715 , H05K2201/09236 , H05K2201/09672 , H05K2201/0979 , H05K2201/098 , H05K2203/0733 , H01L2924/00
摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.
摘要翻译：用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。在一个实施例中，电路板具有布置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。第二组与非导电材料与第一组分离。第一组和第二组的相应迹线可以是堆叠配置。在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。在其它实施例中，迹线构造具有“T形”和“L形”横截面。

10. 发明授权

US07286368B2 System to control effective series resistance of decoupling capacitor 有权
标题翻译：系统来控制去耦电容的有效串联电阻
公开(公告)号：US07286368B2
公开(公告)日：2007-10-23
申请号：US10976716
申请日：2004-10-29
申请人： Dong Zhong , David G. Figueroa , Yuan-Liang Li , Michael M. Desmith
发明人： Dong Zhong , David G. Figueroa , Yuan-Liang Li , Michael M. Desmith
IPC分类号： H05K7/00
CPC分类号： H01L23/50 , H01L2224/16225 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/19106
摘要： According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.
摘要翻译：根据一些实施例，系统包括用于支撑集成电路管芯的集成电路封装。集成电路封装可以包括多个导电触点和去耦电容器。去耦电容器可以包括耦合到多个导电触点中的第一个的正极端子接触焊盘，正极端子接触焊盘包括第一基本上不导电的区域，以及耦合到多个导电触点中的第二个的负极端子接触焊盘的导电触点，负极接触焊盘包括第二基本上不导电的区域。

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