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1. 发明申请

US20070153989A1 Personalized user specific grammars 失效
标题翻译：个性化用户特定语法
公开(公告)号：US20070153989A1
公开(公告)日：2007-07-05
申请号：US11324208
申请日：2005-12-30
申请人： David Howell , Sridhar Sundararaman , David Fong , Frank Seide
发明人： David Howell , Sridhar Sundararaman , David Fong , Frank Seide
IPC分类号： H04M11/00
CPC分类号： H04M3/5307 , H04M2201/405 , H04M2201/60 , H04M2203/253 , H04M2203/4509
摘要： Improved systems and methods are provided for transcribing audio files of voice mails sent over a unified messaging system. Customized grammars specific to a voice mail recipient are created and utilized to transcribe a received voice mail by comparing the audio file to commonly utilized words, names, acronyms, and phrases used by the recipient. Key elements are identified from the resulting text transcription to aid the recipient in processing received voice mails based on the significant content contained in the voice mail.
摘要翻译：提供了改进的系统和方法，用于转录通过统一消息系统发送的语音邮件的音频文件。通过将音频文件与收件人使用的常用词，名称，首字母缩略词和短语进行比较，创建和利用特定于语音邮件收件人的定制语法来转录接收到的语音邮件。从所得到的文本转录中识别关键要素，以帮助接收者基于语音邮件中包含的重要内容来处理接收的语音邮件。

2. 发明申请

US20060259884A1 Merging a hardware design language source file with a separate assertion file 有权
标题翻译：将硬件设计语言源文件与单独的断言文件合并
公开(公告)号：US20060259884A1
公开(公告)日：2006-11-16
申请号：US11125991
申请日：2005-05-10
申请人： David Fong , Zheng Zhang , Qi Chen
发明人： David Fong , Zheng Zhang , Qi Chen
IPC分类号： G06F17/50 , G06F9/45 , G06F17/00
CPC分类号： G06F17/5022
摘要： A method is provided for merging assertions in one input file with hardware description language (HDL) code in another input file to produce an HDL output file. One embodiment, among others, comprises the steps of: copying an assertion identified by an assertion identifier from the first input file; locating a matching assertion identifier within a section of the second input file; and merging the assertion with the section of the second input file to produce a section in the HDL output file.
摘要翻译：提供一种用于将一个输入文件中的断言与另一个输入文件中的硬件描述语言（HDL）代码合并以产生HDL输出文件的方法。一个实施例包括以下步骤：从第一输入文件复制由断言标识符识别的断言; 在所述第二输入文件的一部分内定位匹配的断言标识符; 并将断言与第二个输入文件的部分合并，以产生HDL输出文件中的一个部分。

3. 发明申请

US20050010427A1 Partner management 审中-公开
标题翻译：合作伙伴管理
公开(公告)号：US20050010427A1
公开(公告)日：2005-01-13
申请号：US10617904
申请日：2003-07-11
申请人： Aditya Bhandarkar , David Fong , Eddie Fusaro , Mayank Mehta , Anand Ramanathan , Dharma Shukla , Kumarswamy Valegerepura , Mark Wain , Muralidhara Chilayurl
发明人： Aditya Bhandarkar , David Fong , Eddie Fusaro , Mayank Mehta , Anand Ramanathan , Dharma Shukla , Kumarswamy Valegerepura , Mark Wain , Muralidhara Chilayurl
IPC分类号： G06Q10/00 , G06F17/60
CPC分类号： G06Q10/06 , G06Q10/103
摘要： Partner management systems and methods are disclosed. A designer designs a business process that provides selection criteria for selecting business partners. The business process is compiled and executed by a business process execution engine. During the execution of the business process, the business process execution engine uses the selection criteria to select business partners. The identification of business partners and attributes of the business partners may be modified without modifying the business process.
摘要翻译：披露合作伙伴管理系统和方法。设计师设计一个业务流程，为选择业务伙伴提供选择标准。业务流程由业务流程执行引擎编译和执行。在业务流程执行期间，业务流程执行引擎使用选择标准来选择业务伙伴。业务合作伙伴的身份识别和业务伙伴的属性可能会被修改，而无需修改业务流程。

4. 发明授权

US06791891B1 Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage 有权
标题翻译：测试使用击穿电压的半导体存储单元的薄氧化物的方法
公开(公告)号：US06791891B1
公开(公告)日：2004-09-14
申请号：US10406406
申请日：2003-04-02
申请人： Jack Zezhong Peng , Harry Shengwen Luan , Jianguo Wang , Zhongshan Liu , David Fong , Fei Ye
发明人： Jack Zezhong Peng , Harry Shengwen Luan , Jianguo Wang , Zhongshan Liu , David Fong , Fei Ye
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C16/04 , G11C2029/5002
摘要： A method of testing a memory cell is disclosed. The memory cell has a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, which is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. In order to ensure that the gate oxide underlying the data storage elements are of sufficient quality for programming, the memory cells of a memory array may be tested by applying a voltage across the gate oxide of the data storage element and measuring the current flow. Resultant current flow outside of a predetermined range indicates a defective memory cell.
摘要翻译：公开了一种测试存储单元的方法。存储单元具有围绕诸如栅极氧化物的超薄电介质构成的数据存储元件，其用于通过将超薄电介质压制成击穿（软或硬击穿）来存储信息，以设置泄漏电流水平存储单元。为了确保数据存储元件下面的栅极氧化物具有足够的编程质量，可以通过在数据存储元件的栅极氧化物上施加电压并测量电流来测试存储器阵列的存储单元。在预定范围之外的所得电流表示有缺陷的存储单元。

5. 发明申请

US20070226556A1 Methods and systems for repairing an integrated circuit device 有权
标题翻译：用于修复集成电路设备的方法和系统
公开(公告)号：US20070226556A1
公开(公告)日：2007-09-27
申请号：US11389710
申请日：2006-03-27
申请人： David Fong , Gang Miao
发明人： David Fong , Gang Miao
IPC分类号： G01R31/28
CPC分类号： G01R31/318516 , G01R31/31704
摘要： Provided are systems for repairing an integrated circuit device. The systems include detection logic configured to locate a defective portion of an integrated circuit device, a supplemental integrated circuit component configured to functionally replace the defective portion, and logic configured to identify an interface location. Also provided are methods for repairing an integrated circuit device. The methods include the steps of: identifying a defective portion of an integrated circuit device; disconnecting existing circuit components; and incorporating a supplemental integrated circuit component with the integrated circuit device.
摘要翻译：提供了用于修复集成电路器件的系统。所述系统包括被配置为定位集成电路设备的缺陷部分的检测逻辑，被配置为功能地替换缺陷部分的补充集成电路部件以及被配置为识别接口位置的逻辑。还提供了用于修复集成电路装置的方法。所述方法包括以下步骤：识别集成电路器件的缺陷部分; 断开现有电路部件; 并将集成电路器件与补充集成电路器件相结合。

6. 发明申请

US20070169268A1 Hospital bed 有权
标题翻译：病床
公开(公告)号：US20070169268A1
公开(公告)日：2007-07-26
申请号：US11642047
申请日：2006-12-19
申请人： Guy Lemire , Jean-Paul Dionne , Marco Morin , Richard Pare , Pascal Castonguay , Luc Petitpas , David Fong
发明人： Guy Lemire , Jean-Paul Dionne , Marco Morin , Richard Pare , Pascal Castonguay , Luc Petitpas , David Fong
IPC分类号： A61G7/015 , A47B71/00 , A61G7/018 , A61G7/012
CPC分类号： B60T7/085 , A61G7/005 , A61G7/012 , A61G7/015 , A61G7/018 , A61G7/05 , A61G7/0506 , A61G7/0507 , A61G7/0509 , A61G7/0514 , A61G7/0516 , A61G7/052 , A61G7/0524 , A61G7/0527 , A61G7/0528 , A61G7/08 , A61G7/1046 , A61G2203/16 , A61G2203/20 , A61G2203/32 , A61G2203/36 , A61G2203/42 , A61G2203/44 , A61G2203/46 , A61G2210/50 , A61M5/1415 , B60T17/22 , G16H40/63
摘要： A patient bed includes a base, a patent support supported by the base, and a control system. The patient support includes a pivotal head-end section, with the control system including an actuator to pivot the head-end section and being adapted to control the speed of the actuator and, further, to selectively increase the speed of the actuator to pivot the head-end section at a greater speed.
摘要翻译：患者床包括基座，由基座支撑的专利支持以及控制系统。患者支架包括枢轴头端部分，其中控制系统包括用于枢转头端部分的致动器，并且适于控制致动器的速度，并且还可选择地增加致动器的转速以使枢转头端部分以更高的速度。

7. 发明授权

US07064973B2 Combination field programmable gate array allowing dynamic reprogrammability 有权
标题翻译：组合现场可编程门阵列，允许动态可重新编程
公开(公告)号：US07064973B2
公开(公告)日：2006-06-20
申请号：US10857667
申请日：2004-05-28
申请人： Jack Zezhong Peng , Zhongshang Liu , David Fong , Fei Ye
发明人： Jack Zezhong Peng , Zhongshang Liu , David Fong , Fei Ye
IPC分类号： G11C11/24
CPC分类号： G11C11/405 , G11C11/406 , G11C17/16 , H01L27/0207 , H01L27/108 , H01L27/10894 , H01L27/11807 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/1776 , H03K19/1778
摘要： A cell that can be used as a dynamic memory cell for storing data used in programming a field programmable gate array (FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.
摘要翻译：公开了可用作用于存储用于编程现场可编程门阵列（FPGA）的数据的动态存储单元的单元。该单元包括具有栅极，源极和漏极的选择晶体管，栅极连接到所述写位线，源极连接到浮点节点，漏极连接到行字线。感测装置确定存储在浮点节点上的数据。最后提供由浮点节点控制的开关。

8. 发明申请

US20050275427A1 Field programmable gate array logic unit and its cluster 审中-公开
公开(公告)号：US20050275427A1
公开(公告)日：2005-12-15
申请号：US10916232
申请日：2004-08-11
申请人： Man Wang , Guy Schlacter , David Fong , Jianguo Wang , Jack Peng
发明人： Man Wang , Guy Schlacter , David Fong , Jianguo Wang , Jack Peng
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.

9. 发明授权

US06777757B2 High density semiconductor memory cell and memory array using a single transistor 有权
标题翻译：使用单晶体管的高密度半导体存储单元和存储器阵列
公开(公告)号：US06777757B2
公开(公告)日：2004-08-17
申请号：US10133704
申请日：2002-04-26
申请人： Jack Zezhong Peng , David Fong
发明人： Jack Zezhong Peng , David Fong
IPC分类号： H01L2994
CPC分类号： G11C17/16
摘要： A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor.
摘要翻译：公开了一种由位于列位线和行字线交叉点的晶体管构成的可编程存储单元。晶体管的栅极由列位线形成，其栅极连接到行字线。通过在列位线和行字线之间施加电压电位来编程存储器单元，以在晶体管的栅极下方的衬底中产生编程的n +区。

10. 发明授权

US06670845B1 High D.C. voltage to low D.C. voltage circuit converter 有权
标题翻译：高直流电压到低直流电压电路转换器
公开(公告)号：US06670845B1
公开(公告)日：2003-12-30
申请号：US10197281
申请日：2002-07-16
申请人： David Fong
发明人： David Fong
IPC分类号： G05F324
CPC分类号： G05F1/465
摘要： A high DC voltage to low DC voltage circuit has a first NMOS transistor with the first terminal connected to the source of the high DC voltage and the second terminal connected to supply the low DC voltage. The gate is connected to a middle node of a resistor divider circuit having one end connected to the source of the high DC voltage and the other end to a common node. A plurality of serially connected NMOS transistors has a first end connected to the common node and a second end connected to ground. Each of the NMOS transistors in the plurality of serially connected NMOS transistors has its gate connected to its first terminal and to the second terminal of the immediate adjacent NMOS transistor.
摘要翻译：高直流电压到低直流电压电路具有第一NMOS晶体管，第一端子连接到高直流电压源，第二端子连接以提供低直流电压。栅极连接到电阻分压器电路的中间节点，其一端连接到高DC电压源，另一端连接到公共节点。多个串联的NMOS晶体管具有连接到公共节点的第一端和连接到地的第二端。多个串联NMOS晶体管中的每个NMOS晶体管的栅极连接到其第一端子和连接到紧邻的NMOS晶体管的第二端子。

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